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on Apr 16, 2010
on Apr 19, 2010 by RANDY_RHEA
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It would be nice to have an OscTest port to simulate the small-signal loop gain of the oscillator.
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Apr 19, 2010 10:07 AM
You are absolutely correct. Simulating the open-loop, small-signal transfer and reflection characteristics is critical to understanding oscillator behavior. If the designer only simulates the closed-loop circuit in the oscillation mode, they do not know the gain margin, or if maximum phase slope occurs at the gain peak, or if improved matching could increase the gain margin, or if multiple phase zero crossings occur. In fact, they know little more than with the final constructed oscillator. Yes, it oscillates, but what is the design quality.
The Oscport feature in GENESYS automatically provides the steady-state excitation signal for an HB analysis and unloads that source from the oscillator. But it does not simulate the open-loop, small-signal characteristics. As you suggest, the Oscport feature could be expanded to include two-ports for the open-loop characteristics. However, some type of interface would be required for the user to specify which side (left or right) of the port is the input and which is the output.
For use until such an enhancement is added, an oscillator simulation workspace is attached in this post. This "template.wsx" workspace includes an open-loop, small-signal simulation schematic along with a reuse of that schematic in a closed loop oscillator simulation. I use this template to begin all of my oscillator designs. All I have to do is replace the open-loop schematic with my design. The template workspace includes all the setups for the open-loop analysis, closed-loop HB analysis, a Cayenne time-step simualtion for starting, nonlinear HB noise analysis, and appropriate output graphs. It saves a lot of time. I hope you find it helpful. In a month or two, Agilent will be adding a site to download some 70 or so oscillator workspaces I used while writing the new oscillator book.
Clear skies and high Q
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