Hello Experts,
When I RFDE or RFIC-Dynamic-link any (spectre) circuit that needs compilation of any Verilog-A model or scripts I get an error message of something like this:
***************************************************************************************************
"...
Error detected by hpeesofsim in Compiing Verilog-A based device during netlist parsing.
Error: platform CML complile failure, view the log files:
'xxx.stdout'
'xxx.stderr'
in
.../hpeesof/agilent-model-cache/cml/linux_x86/...
..."
***************************************************************************************************
xxx is the name of a Verilog-A file. I am using ads2005a and cadence2005 on linux.
In fact, I even get this error when I use and follow an Verilog-A example in the doc "Using Verilog-A in RF Design Environment" from ADS. (This example is for RFDE (using ADsim) but I get the same error when I use RFIC Dynamic link.)
This issue is virtually stopping me to use RFDE or RFIC dynamic link  for schematics with any spectre model files (*.scs) that include any verilog-A models (*.va). I've consulted too many documents from ADS and Cadence but still I haven't got any clue....
Since RFDE and RFIC dynamic link are such awesome stuff without which a RFIC engineer can't live I'd really appeciate so so much if you could help me with this!:)
Thank you!
When I RFDE or RFIC-Dynamic-link any (spectre) circuit that needs compilation of any Verilog-A model or scripts I get an error message of something like this:
***************************************************************************************************
"...
Error detected by hpeesofsim in Compiing Verilog-A based device during netlist parsing.
Error: platform CML complile failure, view the log files:
'xxx.stdout'
'xxx.stderr'
in
.../hpeesof/agilent-model-cache/cml/linux_x86/...
..."
***************************************************************************************************
xxx is the name of a Verilog-A file. I am using ads2005a and cadence2005 on linux.
In fact, I even get this error when I use and follow an Verilog-A example in the doc "Using Verilog-A in RF Design Environment" from ADS. (This example is for RFDE (using ADsim) but I get the same error when I use RFIC Dynamic link.)
This issue is virtually stopping me to use RFDE or RFIC dynamic link  for schematics with any spectre model files (*.scs) that include any verilog-A models (*.va). I've consulted too many documents from ADS and Cadence but still I haven't got any clue....
Since RFDE and RFIC dynamic link are such awesome stuff without which a RFIC engineer can't live I'd really appeciate so so much if you could help me with this!:)
Thank you!
This is Nacim Bravo, I will be sending you an email directly to you. This is an known issue and we have a fix for it. The error you see are due to a Linux version and the older Version of ADS. YOu should not see this error if you use a newer version of ADS such as 2006 Update.
Stay tune,
Nacim