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DDR3/4 Compliance, which tests are required for various system HW configs

Question asked by robgrich on Apr 15, 2016
Latest reply on Apr 20, 2016 by algoss
I’m looking for a definitive description of what particular tests are required for the different DDR3/4 HW configurations. i.e. We are discrete DRAM placements embedded on the system PCB, others are DIMMs etc.

I had some DDR3L read parameter failures and it turned out that because the probe points being at the DRAM (interposer) and not at the controller (in our embedded DRAM HW system) those read tests were informative only and not intended for that HW config. Some were written for other HW configurations is my understanding.

Is there a Keysight document that describes which tests are applicable for the different HW configurations, and what tests constitute a JEDEC compliance pass/fail criteria? If not, perhaps you could point me to a JEDEC spec that describes the intended tests for each HW config? Something like SERDES has, AIC and other HW configurations to define the required tests.

In this case we have Read failures, below, in our first DDR4-2400 compliance run, I’m wondering if any of these are not intended to be a JEDEC pass/fail requirement for this system configuration.