I’m looking for a definitive description of what particular tests are required for the different DDR3/4 HW configurations. i.e. We are discrete DRAM placements embedded on the system PCB, others are DIMMs etc.
I had some DDR3L read parameter failures and it turned out that because the probe points being at the DRAM (interposer) and not at the controller (in our embedded DRAM HW system) those read tests were informative only and not intended for that HW config. Some were written for other HW configurations is my understanding.
Is there a Keysight document that describes which tests are applicable for the different HW configurations, and what tests constitute a JEDEC compliance pass/fail criteria? If not, perhaps you could point me to a JEDEC spec that describes the intended tests for each HW config? Something like SERDES has, AIC and other HW configurations to define the required tests.
In this case we have Read failures, below, in our first DDR4-2400 compliance run, I’m wondering if any of these are not intended to be a JEDEC pass/fail requirement for this system configuration.
I had some DDR3L read parameter failures and it turned out that because the probe points being at the DRAM (interposer) and not at the controller (in our embedded DRAM HW system) those read tests were informative only and not intended for that HW config. Some were written for other HW configurations is my understanding.
Is there a Keysight document that describes which tests are applicable for the different HW configurations, and what tests constitute a JEDEC compliance pass/fail criteria? If not, perhaps you could point me to a JEDEC spec that describes the intended tests for each HW config? Something like SERDES has, AIC and other HW configurations to define the required tests.
In this case we have Read failures, below, in our first DDR4-2400 compliance run, I’m wondering if any of these are not intended to be a JEDEC pass/fail requirement for this system configuration.
The correct probing point, for all JEDEC DRAM tests, is at the balls of the DRAM. Since those are generally not accessible, the interposer is the next best choice. You don't say which interposer you are using, or what speed you are running, but if you are running fast enough, and get failures, you probably need to de-embed the interposer using the optional InfiniiSim SW package. That will move the measurement from the interposer edge to the via in the middle of the interposer.
As for your DDR4-2400 tests, you don't indicate if you are have actual read failures on your system, or if the DDR Compliance test is failing. The next steps for each of those conditions is different.
Note that I have seldom seen any systems that pass every JEDEC test. You must look at the results and determine why there was a failure, how bad a failure it was, whether it is fixable, and whether it makes any difference. I have seen released, shipping systems, that run, showing no memory access failures, that fail multiple JEDEC tests.
Al
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