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Problems with Verilog-A

Question asked by iafmember on Oct 14, 2011

I'm new in the area of ADS and Verilog-A and have some Problems.

I should convert ADS FET transistor models, which consists of an SDD, a Current Controlled Votage Source and some resistors, into a Verilog-A model.
The Verilog-A model should be used in ADS as replacement of the old model.

I've read the manual from agilent for converting an SDD into Verilog and I've done the tutorial. But for my model I must made a mistake.

Now I have some errors, since I added one parameter to an resistor. This is my first question.

The simulator reportet these errors:

Error detected by hpeesofsim in Compiling Verilog-A based device.
    Warning: Ordered parameter lists are only supported for Verilog modules.
    Error: Invalid (non-static) initialization for parameter 'R'.

Peace of code:
module TLS_va(g,d,s);
  parameter real UGW = 30;

  //Dummy Wiederstände in Ohm
  real R_dummy1 = 1;
  real R_dummy2 = 1;

  Resistor #(.name("r_dummy1"),.R(R_dummy1))   r_dummy1(sdd3,gnd);                       //line73
  Resistor #(.name("r_dummy2"),.R(R_dummy2))   r_dummy2(sdd5,gnd);
  Resistor #("R_d", R_d, 1) r_drain(d,iccvs);                                                                 //line75
  Resistor #("R_g", R_g, 1)   r_gate(g,sdd1); Resistor #("R_s", R_s, 1)   r_source(gd,s);
  CCVS_VA  ccvs(iccvs,sdd2,gnd,sdd4);
  analog begin


The values for the resistors will be calculated after declaring the resistors, can this lead to this error?
But why occurs this error first after inserting the first parameter "name" for the resistors?

I search also a good book about Verilog-A. It should habe also examples for better learning and understanding.

Can someone help me to solve my problem and/or recommend me a good book?