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some problems about digital modulation

Question asked by kaiwang on Apr 22, 2010
I want to build a design to simulate digital modulation in Digital signal processing network.For example,this is my design for 2PSK.
[img]C:\Documents%20and%20Settings\Administrator\My%20Documents\My%20Pictures\PSK[/img]
After the signal through the component PM_MOD,the component TimedDataWrite has the right 2PSK signal.
[img]C:\Documents%20and%20Settings\Administrator\My%20Documents\My%20Pictures\PSKsinal[/img]
But the component Timedsink's signal have a real part and a image part,and I can not recognize it is a correct signal or not.The real part is the signal i want to modulate and the image part is very small.
At the same time.the signal that TimedDataWrite has can not  be demodulated correctly.
I am confused.  

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