Hello,
Please to meet you guys. I am a newbie RF Engineer assigned to work on 802.15.4 wireless devices. I just have a few fill-in-the-blank questions regarding momentum.
Below is a link to my first set of questions:
link
I also would like to know exactly how do I place my soldermask onto my board? In the entry layer box, there lists a soldermask option. When I click on it, and draw a polygon, where does the solder mask go?
My question is:
1: Suppose I have cond 1 and cond 2 layers. Does the soldermask cover cond 1 or cond 2 or both?
2: How do I draw the soldermask? Do I just extend a rectangle over my cond layer?
3: I tried listing my soldermask in my substrate definition. When I go to the metallization tab, i can map one solder mask layer as a strip/slot/via but not the other.
Is it better to list my soldermask as a substrate layer, map it as a strip or just draw it in layout?
I am designing a stacked patch antenna. the soldermask placed on the radiators during fab/production time is critical in my desing since the dielectric coating detunes my device.
Any help will be greatly appreciated.
Thanks.
Please to meet you guys. I am a newbie RF Engineer assigned to work on 802.15.4 wireless devices. I just have a few fill-in-the-blank questions regarding momentum.
Below is a link to my first set of questions:
link
I also would like to know exactly how do I place my soldermask onto my board? In the entry layer box, there lists a soldermask option. When I click on it, and draw a polygon, where does the solder mask go?
My question is:
1: Suppose I have cond 1 and cond 2 layers. Does the soldermask cover cond 1 or cond 2 or both?
2: How do I draw the soldermask? Do I just extend a rectangle over my cond layer?
3: I tried listing my soldermask in my substrate definition. When I go to the metallization tab, i can map one solder mask layer as a strip/slot/via but not the other.
Is it better to list my soldermask as a substrate layer, map it as a strip or just draw it in layout?
I am designing a stacked patch antenna. the soldermask placed on the radiators during fab/production time is critical in my desing since the dielectric coating detunes my device.
Any help will be greatly appreciated.
Thanks.
However, a co-worker suggested that a mesh size that is to fine will introduce false valleys into the s-parameter plots. I don't want my mesh too course, but I also want accurate infromation for my stacked patch design.