Hello.
I have a plannar on-chip inductor that is built on top of a substrate that consists of bulk silicon of sheet resistance 1 KOhm/sq and thin p-layer of sheet resistance 7 Ohm/sq on top of that.
In the RFDE substrate definition file I modeled the thin p-layer in two different ways, and ran one simulation foe each case:
(1) p-layer is defined as an interface layer on top of bulk silicon.
(2) p-layer is defined as an extra metal layer with the same sheet resistance as p-layer and at the same vertical distance away from the actual process metal layers used for the inductor. This extra metal layer is connected to the substrate using multiple low ohmic vias to model the actual physical connection between the bulk and p-layer
Both cases give very different results, with case (2) showing a much lower quality factor for the inductor. I am inclined to trust the results of case (1) more, but I cannot really explain why.
Any ideas on that?
Your fast response is greatly appreciated.
/Shadi Yousef
I have a plannar on-chip inductor that is built on top of a substrate that consists of bulk silicon of sheet resistance 1 KOhm/sq and thin p-layer of sheet resistance 7 Ohm/sq on top of that.
In the RFDE substrate definition file I modeled the thin p-layer in two different ways, and ran one simulation foe each case:
(1) p-layer is defined as an interface layer on top of bulk silicon.
(2) p-layer is defined as an extra metal layer with the same sheet resistance as p-layer and at the same vertical distance away from the actual process metal layers used for the inductor. This extra metal layer is connected to the substrate using multiple low ohmic vias to model the actual physical connection between the bulk and p-layer
Both cases give very different results, with case (2) showing a much lower quality factor for the inductor. I am inclined to trust the results of case (1) more, but I cannot really explain why.
Any ideas on that?
Your fast response is greatly appreciated.
/Shadi Yousef
Sep 18, 2007 8:37 PM