# Some general Ptolemy dialog

Question asked by glcr on May 6, 2003
Some interesting general questions and answers concerning Ptolemy......  :)

1)  What is the proper conversion technique going from the digital HDL domain back to the analog domain?  Right now I'm using a gain stage to recreate the proper voltage swing followed by a FixToTimed source converter.

ANS: 1)  The proper conversion technique for going from fixed point to "analog" is to use the FixToTimed converter so you are doing this correctly.  Remember the Tstep on this component will effectively establish the sampling rate for the conversion, limiting your signal to a BW=1/(2*Tstep).  As for establishing the correct "voltage" value, you can do it the way you have described or you can follow the FixToTimed conversion with a GainRF block, which will give you any arbitrary gain.

2)  What is the proper conversion technique going from the analog domain into the digital HDL domain?  Currently, I'm using a TimedToFix converter with OutputPrecision = 8.0 with overflow and roundfix set to various settings depending on how the signal is behaving.  The output of the data converter is fed into a gain stage set to .5 to approximate a 0 to 1 volt swing.

ANS:  2) The proper conversion technique for going from "analog" to fixed point is to use the TimedToFix as you have done.  The numeric precision you set on this block will determine the "dynamic range" of the conversion, limiting your input signal range to the converter.  Since many digital designs incorporate two's compliment math, the signal should be normalized to a voltage range using a fixed point scaling as you describe, or by preceding the TimedToFix with an "analog" gain block that will scale the "voltage" for you.  Also be careful when setting the OverflowHandler type.  If it is set to wrapped the twos compliment numbers will wrap around giving you odd results.  These are the considerations one has to make when doing these types of designs.

3)  I'm getting signal inversion when going from through the TimedToFix converter with outputprecision = 1.0.  In other words, instead of getting a signal that is 0 or 1, I'm getting a signal that's 0 or -1.

ANS:  3) This component uses twos compliment math so the 1.0 format will give you -1 or 0 since the left most bit represents sign.  Change to 2.0 and you should see the result you desire.

4)  I have a DSP "Data" (timed) block generating a clock pattern.  I couldn't get the clock block to function properly, but I imagine that is caused by the above issues.  I am curious as to why I see a voltage swing from -2 to +2 instead of 0 to 1.  The settings for the block are:  TStep=100ps, BitTime=50ns, Pattern = 0x555555....., Type=Prbs,SequencePattern=8, and repeat=yes.  I manipulated this signal through many blocks to get the proper levels (0 to 2.5v).

ANS:  4) What you are seeing as far as a "voltage" swing is due to a simple use model of these Timed components.  Each component that is of the Timed type will scale it's output with the expectation that the following component will have a terminating resistor that will make the signal amplitude correct.  The data source you are using scales it's output to -2 to 2 "volts" so that when you place another timed component, or a resistor to ground along with an un-timed component (i.e. the TimedToFix converter) the signal will become -1 to +1 volts.  Sorry this caused you confusion.   :-[  The other thing about this the Timed data source is it is an NRZ source, so you will not see 0 to 1.  Lastly, the Timed data source is a sampled source, so there will be a fixed number of samples per bit time as defined by the ratio of BitTime/Tstep.

Some general comments, you may have noticed that I placed voltage and analog in quotes above.  The reason I did this is Ptolemy does not simulate currents and voltages.  :D  They are only analogies when using the Timed components.   Another comment is if you are trying to generate zeros and ones to stimulate a simulation, there are other non-Timed, or Numeric sources that will give you binary 0s and 1s as a sequence with only one sample per bit.  This may make more sense for what you are trying to do.

- Frank Ditore, Sr. Applications Engineer, EEsof EDA