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Cayenne (Transient) Example

Question asked by pkarasev on Oct 12, 2006
This example shows a setup and analysis of logic gates with parasitic capacitance combined into an SR latch using the transient simulator. Reset fires first to put the circuit in a stable state, then flipping set high latches the output high until another reset.

Note that the propagation delay of the latch can be directly measured from the datasets or graph (1.5 ns for set and 0.2 ns for reset  in this case). Also the effect of decreasing pulse widths can be observed; if the set width is lowered to .2 ns, the circuit can be seen to enter an unstable oscillatory state.

[file]sr_latch.wsx[/file]

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