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producing .cdc file with core generator or Xilinx EDK

Question asked by Souhaibe_Forums on Apr 2, 2008
Latest reply on Apr 2, 2008 by Souhaibe_Forums
Core Generator or EDK does not produce the .cdc file required for automated signal name entry in the logic analyzer. If I use Core Generator or EDK instead of Core Inserter is there a way for me to manually make my own .cdc file?  

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