Logic and Protocol Analyzers
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producing .cdc file with core generator or Xilinx EDK
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on Apr 2, 2008
on Apr 2, 2008 by Souhaibe_Forums
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Core Generator or EDK does not produce the .cdc file required for automated signal name entry in the logic analyzer. If I use Core Generator or EDK instead of Core Inserter is there a way for me to manually make my own .cdc file?
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Apr 2, 2008 12:35 PM
Yes. You have two different options.
1. Run Core Generator or EDK and set the core parameters. These tools will make a .cdc file that you can use as a template. Open the .cdc file template using a text editor. Modify the bank input signal names so that they reflect the signal path name of the probed net.
2. The FPGA dynamic probe application reads core parameters via JTAG when the user initiates a JTAG communication session with the â€œConnect Cableâ€ button. One of the parameters the logic analyzer reads is the number of signal banks, and the number of signals per bank. The logic analyzer application uses generic names for each signal when a .cdc file is not loaded. For example signal 0 is generically labeled as ATC â€“ 0 (AgilentTrace Core bit 0).
On the logic analyzer, you can manually rename each ATC name with the signal names from your design. The FPGA dynamic probe application will remember name changes you made for each bank.
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