I want to determine the total delay time through two-16720A Master/slave Clock outputs. I am using an external clock for his 16720A pattern output. I am debuging a DUT timing problem which I need to know how much delay time from the 16720A Clock input to the pattern generator output using the LVDS Pobs. What is the delay time from the Clock input to the 16720A Master pattern output and what is the delay time from the Clock input to 16720A Slave Module pattern output?
I don’t want to add delay time to the Clock to pattern output.
I don’t want to add delay time to the Clock to pattern output.
There will be a significant delay between EXTERNAL CLOCK IN and CLOCK OUT at the clock pod due to cable length and circuitry (about 30 ns). This value is not characterized and should be measured on the individual system, with a scope if you are trying to get the exact value.
The clock delay circuit in the 16720 is 7 ns in 500ps steps. The clock relationship to data starts at -2ns and delays to +5 ns beyond data. These numbers are approximate (not calibrated) and are intended to allow the user to skew data around the clock edge to meet the setup and hold characteristics of different devices.
To get a larger clock to data offset, you can use the falling edge of the clock (or rising edge of the inverted clock, both are available) to clock your circuit. Now data is offset by 1/2 the clock period +- clock delay.
The CLOCK OUT is the same relative to data whether using internal or external source clocking.
Adding cable length to clock or data will add delay.
Clock delay works with EXT clock IN as well as INT clock. This is implemented as a chain of gates (delays).
The clock out delay is with reference to all channels as a block.
Internal Clock Period:
Programmable from 1 MHz to 300 MHz in 1 MHz steps.
External Clock Period:
DC to 300 MHz.
An advantage of using an external clock is that you synchronize the vector output of the pattern generator to the system under test. The 16720A passes external clocks without any added jitter or distortion. External clocks can have tightly controlled jitter and frequency specifications.
No matter which clock source is used, vectors are always output on the rising edge of the clock.
The first clock edge starts the 16720A. The 16720A will begin sending data with the next clock cycle.