I have a Virtex 2 FPGA, using dynamic probe (B4655A), I am wondering how does the test bank work and can I use a different clock on each bank or do I need a clock with each bank?
The core contains test generation circuitry to stimulate the signal banks and output pins. With this active data running, the logic analyzer invokes the Eye Finder feature to automatically adjust for variances in path delays through the core to the acquisition system on the logic analyzer.
In terms of separate clock banks, timing cores do not have a clock, because information is sampled using the logic analyzer’s internal clock. For state cores, the ATC2 core has a master clock that is used for all banks. Multiple ATC2 cores can be used for multiple clock domains.
In terms of separate clock banks, timing cores do not have a clock, because
information is sampled using the logic analyzer’s internal clock. For state cores, the ATC2 core has a master clock that is used for all banks. Multiple ATC2 cores can be used for multiple clock domains.