FPGA dynamic probe was designed to have minimal intrusion in both the design flow and the design itself. Here are the top areas where the FPGA dynamic probe solution will save you work and time, even if you already use your own MUXes.
1. FPGA dynamic probe does not require you to modify your HDL code when using Core Inserter flow. Teams not using FPGA dynamic probe must modify HDL code to include MUXes.
2. Control of which signals are presented for measurement is done from the logic analyzer in about a second (only 2 mouse clicks). Teams not using FPGA dynamic probe must design in special capability (such as changing register values) to change which signals are presented to IO pins for measurement.
1. FPGA dynamic probe does not require you to modify your HDL code when using Core Inserter flow. Teams not using FPGA dynamic probe must modify HDL code to include MUXes.
2. Control of which signals are presented for measurement is done from the logic analyzer in about a second (only 2 mouse clicks). Teams not using FPGA dynamic probe must design in special capability (such as changing register values) to change which signals are presented to IO pins for measurement.