Logic and Protocol Analyzers
to create and rate content, and to follow, bookmark, and share content with other members.
Core Inserter VS core generator in Xilinx FPGA dynamic probe
Question asked by
on Apr 2, 2008
on Apr 2, 2008 by Souhaibe_Forums
Show 0 Likes
I have a Xilinx Virtex II pro, are there advantages to using Core Inserter versus Core Generator or EDK?
No one else has this question
Mark as assumed answered
This content has been marked as final.
Show 1 comment
(Required, will not be published)
Apr 2, 2008 12:24 PM
Yes. Core Inserter also produces a .cdc file. This is a small file listing the signal inputs to the ATC2 core. This file is used to automatically synchronize design signal names with logic analysis bus and signal names. Agilent recommends using Xilinx Core Inserter so you can take advantage of signal-name mapping. Xilinx has a stimulus core known as VIO. This core can only be created and placed in a design
using Core Generator. For a single design that contains both a VIO core and an ATC2, Core Generator must be used.
Show 0 Likes
Retrieving data ...
34461A DMM USB Connection Error
U1253B display problem
Measuring Cycle-to-Cycle Jitter
synchronization between the waveform transmission and data capturing
Issues connecting to M8190A