Yes. Core Inserter also produces a .cdc file. This is a small file listing the signal inputs to the ATC2 core. This file is used to automatically synchronize design signal names with logic analysis bus and signal names. Agilent recommends using Xilinx Core Inserter so you can take advantage of signal-name mapping. Xilinx has a stimulus core known as VIO. This core can only be created and placed in a design using Core Generator. For a single design that contains both a VIO core and an ATC2, Core Generator must be used.
using Core Generator. For a single design that contains both a VIO core and an ATC2, Core Generator must be used.