AnsweredAssumed Answered

number of vias vs. simulation time

Question asked by caburak on Oct 27, 2008
Latest reply on Nov 4, 2008 by ALEPEREZ
Hi,

I have been trying to optimize an inductor in a modern deep-submicron CMOS technology. Since the via resistance is pretty important, I add a stacked via structure from low-level metal (metal-1) to top metal (metal-8). However, when I add the sea of via (let us say 10x10 vias at per metal layer), the simulation takes so much time (days).

I know vias cause increased simulation time. However, the vias I used are regular structures. They repeat again and again in the same layer. Is there a trick to reduce the simulation time for this kind of regular/symmteric structures in Momentum environment?

Thanks in advance.  

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