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Reference Offset of CPW Ports

Question asked by fcolomb on May 30, 2006
Latest reply on May 30, 2006 by ALEPEREZ
Ran into unexpected results with Reference Offset of CPW ports.

First simulated 500um long uniform section of CPW line.  Center width=60um, gap=30um, substrate thickness=360um, epsr=9.66, conductor backed; all ideal conductors; 10GHz.  Momentum: S21=1.000/-13.840deg. ADS CPWG &CPWSUB schematic simulation: S21=1.000/-13.898deg.  No problem.

Then added 250um reference offset to both ports in Momentum using Port Editor.  This in essence should result in an ideal through since the reference planes meet in the middle. Thus, expecting S21=1.  Momentum S21=1.000/-27.734deg.  What is that?

Please advise.  Need to do things differently, known problem, work around...?