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Reference Offset of CPW Ports

Question asked by fcolomb on May 30, 2006
Latest reply on May 30, 2006 by ALEPEREZ

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Ran into unexpected results with Reference Offset of CPW ports.

First simulated 500um long uniform section of CPW line. Center width=60um, gap=30um, substrate thickness=360um, epsr=9.66, conductor backed; all ideal conductors; 10GHz. Momentum: S21=1.000/-13.840deg. ADS CPWG &CPWSUB schematic simulation: S21=1.000/-13.898deg. No problem.

Then added 250um reference offset to both ports in Momentum using Port Editor. This in essence should result in an ideal through since the reference planes meet in the middle. Thus, expecting S21=1. Momentum S21=1.000/-27.734deg. What is that?

Please advise. Need to do things differently, known problem, work around...?

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ALEPEREZ

May 30, 2006 4:21 AM

Conductor backed CPW line models in slot have known limitations regarding well-confined CPW modes. The port solver may not be able to correctly account for any parallel plate mode parasitics that might be excited. Best thing would be to send your model to the EEsof Tech Support group in your region and have them look at it in detail.

Or you can remove the infinite bottom ground and validate the deembedding there to confirm that it in principle works.

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fcolomb May 30, 2006 5:36 AM

Thank you.

Another observation. The phase delay with reference offset is double that of the no offset case. If I enter a negative reference offset of -250um, then Momentum S21=1.000/0.055deg which is what it should have been for and ideal through.

Could it be that there is a sign error in the code for the reference offset?

Anyone else seen this before?

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ALEPEREZ

May 30, 2006 7:30 AM

It's always possible, but you could save some time in reproducing this by sending your project in to the appropriate support email address. Thanks!

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ALEPEREZ May 30, 2006 4:21 AM
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Conductor backed CPW line models in slot have known limitations regarding well-confined CPW modes. The port solver may not be able to correctly account for any parallel plate mode parasitics that might be excited. Best thing would be to send your model to the EEsof Tech Support group in your region and have them look at it in detail.

Or you can remove the infinite bottom ground and validate the deembedding there to confirm that it in principle works.
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fcolomb May 30, 2006 5:36 AM
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Thank you.

Another observation. The phase delay with reference offset is double that of the no offset case. If I enter a negative reference offset of -250um, then Momentum S21=1.000/0.055deg which is what it should have been for and ideal through.

Could it be that there is a sign error in the code for the reference offset?

Anyone else seen this before?
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ALEPEREZ May 30, 2006 7:30 AM
Mark Correct
Correct Answer
It's always possible, but you could save some time in reproducing this by sending your project in to the appropriate support email address. Thanks!
Like • Show 0 Likes0
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Reference Offset of CPW Ports

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