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Instantiating Spice Primitives in Verilog-A

Question asked by TNAKA on May 12, 2006
Hi.

In Cadence Spectre, as we can instantiate Verilog-A modules in other Verilog-A modules, we can instantiate Spectre and SPICE masters in Verilog-A modules. We can also instantiate models and subcircuits in Verilog-A modules.

But it seems that ADS(2005A-MSR2) doesn't have these abilities.

The following Verilog-A module instantiates two Spectre primitives: a resistor and an isource.

module ri_test (pwr, gnd) ;
electrical pwr, gnd ;
parameter real ibias = 10u, ampl = 1.0 ;
electrical in, out ;
resistor #(.r(100K)) RL (out, pwr) ;
isource #(.dc(ibias)) Iin (gnd, in) ;
endmodule

But ADS can't accept this module.

In some cases, we need to use Analog primitives such as resistor, tline, vsource, inductor, capacitor, etc.

For example, we have to use tline instead of absdelay(), since absdelay() is not valid for small-signal analysis.
And it is useful to use resistor primitives in regarding noise modeling.

Why doesn't ADS have these abilities ?
???  

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