Using the DSA 91304A with jitter analysis software. Clock recovery is performed with a 2nd order pll. The data is PRBS7.
Does the software pll bandwidth automatically change if the input goes from PRBS7 to clock (=D10.2 pattern). For example in a real clock-data recovery design, if the pll bandwidth=10Mhz for PRBS7 , the effective pll bandwidth wil double to ~ 20Mhz if the pattern is change to D10.2 .
Does this occur for the software pll ?
Does the software pll bandwidth automatically change if the input goes from PRBS7 to clock (=D10.2 pattern). For example in a real clock-data recovery design, if the pll bandwidth=10Mhz for PRBS7 , the effective pll bandwidth wil double to ~ 20Mhz if the pattern is change to D10.2 .
Does this occur for the software pll ?
You may understand the following already but it might be useful to note anyway:
In a hardware pll there is a phase detector which produces an error signal proportional to the phase difference between it's 2 inputs (a local oscillator and the incoming data signal). This error signal is usually a series of pulses with the width of the pulses corresponding to the phase error. This error signal is then run through a low-pass filter before being fed to the control input of the local oscillator so that we don't drive the oscillator nuts with high frequency modulation. Instead there is a relatively smooth error signal whose amplitude represents the changing frequency of the incoming data relative to the local oscillator. This filter loop bandwidth is nominally what sets the loop bandwidth of the pll.
Now if you think about feeding a 1010 (D10.2) pattern into the pll, there will be a pulse in the error signal for every clock cycle (100% transition density). However if you start to lower the transition density (PRBS has 50%) then you will only get pulses in the error signal on average every 2 clock cycles. After going through the low pass filter you would end up with a lower amplitude error signal for the same phase modulation profile on the incoming PRBS data signal.
Some hardware clock recovery designs such as those used in our 83496B and 86108B clock recovery modules have controls to measure the transition density of the incoming data and thus use that information to correctly set the loop bandwidth. This is done by setting a gain term inside the pll loop. However note that this is not dynamic and so a pattern with long areas of low transition density and high transition density will still end up causing the loop bandwidth to vary as the data comes in.
In the Infiniium software clock recovery the process is much different. I believe that we interpolate between the missing edges in the pattern so the gain term does not have to be adjusted to compensate for that.