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clock recovery pll in jitter analysis

Question asked by jdl54 on Jul 15, 2011
Latest reply on Feb 9, 2012 by jonno
Using the DSA 91304A with jitter analysis software. Clock recovery is performed with a 2nd order pll. The data is PRBS7.
Does the software pll bandwidth automatically change if the input goes from PRBS7 to clock (=D10.2 pattern). For example in  a real clock-data recovery design, if the pll bandwidth=10Mhz for PRBS7 , the effective pll bandwidth wil double to ~ 20Mhz if the pattern is change to D10.2 .
Does this occur for the software pll ?