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FPGA timing with ATC2 cores
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on Jan 19, 2007
on Jan 26, 2007 by Brig Asay
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One other question. What timing impact should I anticipate using Agilent's ATC2 core with a Spartan 3 device? Also, should I plan on removing the core when I ship or should I leave it in?
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Jan 26, 2007 2:15 PM
I've been working with Agilent's FPGA dynamic probe on both their logic analyzers and MSOs since '04. Here's the skinny.
It saves tons of time and is very usable. However, there is an upfront cost in designing in an ATC2 using ChipScope Pro core inserter. Plan on spending 30min to 60min on this --- with a saving of mulitple hours later.
Leaving in the core:; doesn't really matter. The ATC2 core is in "sleep" mode and doesn't consume power until accesses via JTAG.
Timing: Minimal impact. I was amazed. The ATC2 core using a "multistage pipeline" that is covered well in the product FAQ (
and then click on the FAQ).
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