I am trying to design on-chip spirals using the Momentum Optimizer. I happen to be using a process that allows modified 45degree Manhattan layout and intend to exploit this by using octogonal spirals. These are hard to draw accurately when pushing rectangles manually, requiring a lot of geometry to go on to the next coil. Thus, I shiver at the thought of not only getting all my coils drawn, using several layers and everything, but then going through it all again to make a perturbed design (this should be a real NIGHTMARE with octogons).
As this process involves a lot of geometry, and as computers do math a lot faster than I do, I was thinking a parameterized artwork cell would do the job for me quite easily once I get a good layout algorithm down.
Now, I'm hoping I could use the Graphical Cell Compiler to get the parameterized artwork cell created, but I have doubts it will really be sophisticated enough to properly and easily handle 45degree geometry. So, I will likely end up writing raw AEL code.
One thing that would be cool about this approach is that I could program the cell to change the number of vias used to connect to my undercoil bridge. This is extremely desirable as VLSI technologies always use identically sized clusters of vias instead of single large vias which board technologies often allow. However, answers in the last thread about optimization with, what was it the Design Scaler tool?...(can't see threads while writing one), suggest this isn't possible and the optimizer absolutely insists on like topologies under all conditions. I guess to formulate a question with this paragraph I'd ask, can the optimizer be talked into using the parameters of a parameterized artwork cell and stick to them even if it changes the topology by changing the number of shapes and, hence, the number of vertices? If not, I'll find an approximation to the real VLSI process using a single via.
But the gist of what I'm asking is this:
* Can the Momentum Optimizer create initial and perturbed designs using parameterized artwork?
* Can the Optimizer be convinced to use the parameterized artwork cell's own parameters?
* Can the Optimizer stick to these parameters through its various simulations even if they change the layout topology, which is to ask, can the optimizer be convinced to *use* the parameterized cell to create its iterative layouts? I suppose I want to do it Cadence style, putting variables into an object's form parameters and optimizing on those variables.
If using parameterized cells could provide a hack to get the optimizer to handle varying topologies, I'm sure a lot of people would be interested, as it would circumvent one of Momentum's sticking points in providing accurate VLSI simulations. That one's definately on my wish list!
Thanks in advance for any help you can provide me on this issue.
vgreer
As this process involves a lot of geometry, and as computers do math a lot faster than I do, I was thinking a parameterized artwork cell would do the job for me quite easily once I get a good layout algorithm down.
Now, I'm hoping I could use the Graphical Cell Compiler to get the parameterized artwork cell created, but I have doubts it will really be sophisticated enough to properly and easily handle 45degree geometry. So, I will likely end up writing raw AEL code.
One thing that would be cool about this approach is that I could program the cell to change the number of vias used to connect to my undercoil bridge. This is extremely desirable as VLSI technologies always use identically sized clusters of vias instead of single large vias which board technologies often allow. However, answers in the last thread about optimization with, what was it the Design Scaler tool?...(can't see threads while writing one), suggest this isn't possible and the optimizer absolutely insists on like topologies under all conditions. I guess to formulate a question with this paragraph I'd ask, can the optimizer be talked into using the parameters of a parameterized artwork cell and stick to them even if it changes the topology by changing the number of shapes and, hence, the number of vertices? If not, I'll find an approximation to the real VLSI process using a single via.
But the gist of what I'm asking is this:
* Can the Momentum Optimizer create initial and perturbed designs using parameterized artwork?
* Can the Optimizer be convinced to use the parameterized artwork cell's own parameters?
* Can the Optimizer stick to these parameters through its various simulations even if they change the layout topology, which is to ask, can the optimizer be convinced to *use* the parameterized cell to create its iterative layouts? I suppose I want to do it Cadence style, putting variables into an object's form parameters and optimizing on those variables.
If using parameterized cells could provide a hack to get the optimizer to handle varying topologies, I'm sure a lot of people would be interested, as it would circumvent one of Momentum's sticking points in providing accurate VLSI simulations. That one's definately on my wish list!
Thanks in advance for any help you can provide me on this issue.
vgreer
ADS2002C introduced a concept called Layout Components which is a far more powerful method for parameterizing and optimizing circuits than the older empipe3D optimizer. To use AEL artwork macros (which is what you really want here, not GCC), you should search the Agilent Knowledge Center (using the keyword "spiral macro") for an example that contains a large number of prewritten artwork macros. This URL may work:
http://edasupportweb.soco.agilent.com/cgi-bin/show.pl?id=8837
This is one of the best Examples I have ever seen in terms of depth and thoroughness, and it includes various spiral topologies, intertwined transformers, etc. This makes writing your own a *lot* easier.
Once you have the artwork macro in place, you tie it to a subnetwork. This is the network you will then use for creating a parameterized Layout Component. With LC's, you insert symbols that look just like the layout into a schematic and wire it up with whatever else you need (other passive and/or active devices). Then you can define a true EM-circuit co-optimization where parameters for either the LC's or any other circuit elements can be optimized in one step.
If you can't figure out how to do all this, the best place to go is Agilent EEsof Technical Support for bootstrap help. We are talking about fairly complex and advanced algorithms and UI controls, and it's impossible to demonstrate them via this forum.
URL updated by support_admin @ Mar 3 2004