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Affects of ATC2 on timing and signal routing
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on Apr 2, 2008
on Apr 2, 2008 by Souhaibe_Forums
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I am using a Spartan 3E Xilinx FPGA, what effect does the ATC2 core have on my designâ€™s timing? Does loading the ATC2 affect my signal routing?
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Apr 2, 2008 1:28 PM
The ATC2 core is a firm core. The core will not affect the synthesis of the design when you create and insert the core using Core Inserter. The inclusion of an ATC2 core in the design may affect the placement and routing of the overall FPGA design. In typical applications, the effect should be small. The effect on design timing will depend on how the core is configured (for example, the number of signals you choose per bank and the total number of banks) and the number of resources available on the particular FPGA device being used.
The ATC2 state core includes a flop that registers data. The ATC2 core adds one additional load (flop) on each signal probed. This load will be factored into routing to meet user specified timing constraints. This flop helps the tools meet timing constraints for most types of designs.
The ATC2 timing core adds a wire load for each signal probed. This wire load is a false path that is ignored during place and route of the design. Hence, the timing core has minimal-to-no effect on design timing. You can determine the skew between signals by viewing the delay file generated by the design tools to estimate this difference.
Once the ATC2 core (either state or timing core) is in the design, switching from signal bank to signal bank does not change design timing, as all connections have been already made.
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