I want to build and insert and Agilent Trace Core 2 (ATC2) into my design, but I am not sure about the its size and how many of my device resources does it take?
Each input signal adds roughly 1 slice to the size of the ATC2 core. The ATC2 cores have been designed to be as small as possible. For example, an ATC2 state core configured with 8 signal banks and 80 signals per bank consumes about 94 slices, or less than 1 percent of the resources on a Xilinx XCV2000 device. The actual core size depends on parameters chosen such as:
1. Core type: state, state with pin compression or timing 2. Number of pins 3. Number of signal banks.
1. Core type: state, state with pin compression or timing
2. Number of pins
3. Number of signal banks.