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Flip Flops in Xilinx FPGA dynamic probe timing core
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on Apr 2, 2008
on Apr 2, 2008 by Souhaibe_Forums
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In my Xilinx FPGA dynamic probe I see flip flops in my timing core is this ok? Where do they come from?
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Apr 2, 2008 9:42 AM
The path from the probed signal to the output pad is not registered in the timing core. This path has only a combinatorial mux connected to output pads. The flip flops in the timing core are used only for core control and status.
An example of a core controlsignal is the bank mux select. These control and status flip flops are registered by the JTAG TCK clock, not a design clock. Therefore these flip flops are part of the low-speed circuit used by the logic analyzer to control and poll the core.
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