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About Interconnect Test Signature

Question asked by wangkai on Nov 30, 2009
How to identify the counting sequence bits, anti aliasing bits and power bits in interconnect test signatures.
!    3   3     U1B4.M3   TP_PLD_LEFT<19> '0111010001'
!    3   3     U1B4.M3   TP_PLD_LEFT<19> 'LHHHLHLLLH' ! PO Monitor
!   11  11     U1B4.M2   TP_PLD_LEFT<17> '0110110100'
!   11  11     U1B4.M2   TP_PLD_LEFT<17> 'LHHLHHLHLL' ! PO Monitor
!   19  19     U1B4.L2   TP_PLD_LEFT<15> '0110010101'
!   19  19     U1B4.L2   TP_PLD_LEFT<15> 'LHHLLHLHLH' ! PO Monitor
!   25  25     U1B4.K2   TP_PLD_LEFT<13> '0101111000'
!   25  25     U1B4.K2   TP_PLD_LEFT<13> 'LHLHHHHLLL' ! PO Monitor
!   37  37     U1B4.J2   TP_PLD_LEFT<11> '0101011001'
!   37  37     U1B4.J2   TP_PLD_LEFT<11> 'LHLHLHHLLH' ! PO Monitor
!   53  53     U1B4.J1   TP_PLD_LEFT<10> '0100111100'
!   53  53     U1B4.J1   TP_PLD_LEFT<10> 'LHLLHHHHLL' ! PO Monitor
!   59  59     U1B4.G2   TP_PLD_LEFT<8>  '0100011101'
!   59  59     U1B4.G2   TP_PLD_LEFT<8>  'LHLLLHHHLH' ! PO Monitor
!   67  67     U1B4.E2   TP_PLD_LEFT<6>  '0011110000'
!   67  67     U1B4.E2   TP_PLD_LEFT<6>  'LLHHHHLLLL' ! PO Monitor
!   71  71     U1B4.C2   TP_PLD_LEFT<4>  '0011010001'
!   71  71     U1B4.C2   TP_PLD_LEFT<4>  'LLHHLHLLLH' ! PO Monitor
!   77  77     U1B4.D2   TP_PLD_LEFT<1>  '0010110100'
!   77  77     U1B4.D2   TP_PLD_LEFT<1>  'LLHLHHLHLL' ! PO Monitor
!   81  81     U1B4.B2   NC_CPLD_B2_DNU  '0001011001'
!   81  81     U1B4.B2   NC_CPLD_B2_DNU  'LLLHLHHLLH' ! PO Monitor
!   91  91     U1B4.B3   TP_PLD_RIGHT<14>'1101011001'
!   91  91     U1B4.B3   TP_PLD_RIGHT<14>'HHLHLHHLLH' ! PO Monitor
!  119 119     U1B4.B8   TP_PLD_RIGHT<20>'1101111000'
!  119 119     U1B4.B8   TP_PLD_RIGHT<20>'HHLHHHHLLL' ! PO Monitor
!  141 141     U1B4.B10  TP_PLD_RIGHT<22>'1110010101'
!  141 141     U1B4.B10  TP_PLD_RIGHT<22>'HHHLLHLHLH' ! PO Monitor
!  157 157     U1B4.B11  TP_PLD_RIGHT<24>'1110110100'
!  157 157     U1B4.B11  TP_PLD_RIGHT<24>'HHHLHHLHLL' ! PO Monitor
!  167 167     U1B4.C12  TP_PLD_RIGHT<0> '1001011001'
!  167 167     U1B4.C12  TP_PLD_RIGHT<0> 'HLLHLHHLLH' ! PO Monitor
!  175 175     U1B4.C13  TP_PLD_RIGHT<2> '1001111000'
!  175 175     U1B4.C13  TP_PLD_RIGHT<2> 'HLLHHHHLLL' ! PO Monitor
!  183 183     U1B4.D13  TP_PLD_RIGHT<4> '1010010101'
!  183 183     U1B4.D13  TP_PLD_RIGHT<4> 'HLHLLHLHLH' ! PO Monitor
!  191 191     U1B4.E13  TP_PLD_RIGHT<6> '1010110100'
!  191 191     U1B4.E13  TP_PLD_RIGHT<6> 'HLHLHHLHLL' ! PO Monitor
!  199 199     U1B4.F13  TP_PLD_RIGHT<7> '1011010001'
!  199 199     U1B4.F13  TP_PLD_RIGHT<7> 'HLHHLHLLLH' ! PO Monitor
!  201 201     U1B4.F14  TP_PLD_RIGHT<8> '1011110000'
!  201 201     U1B4.F14  TP_PLD_RIGHT<8> 'HLHHHHLLLL' ! PO Monitor
!  207 207     U1B4.G13  TP_PLD_RIGHT<9> '1100011101'
!  207 207     U1B4.G13  TP_PLD_RIGHT<9> 'HHLLLHHHLH' ! PO Monitor
!  227 227     U1B4.J13  TP_PLD_RIGHT<10>'1100111100'
!  227 227     U1B4.J13  TP_PLD_RIGHT<10>'HHLLHHHHLL' ! PO Monitor
!  235 235     U1B4.M13  TP_PLD_RIGHT<29>'1111010001'
!  235 235     U1B4.M13  TP_PLD_RIGHT<29>'HHHHLHLLLH' ! PO Monitor
!  245 245     U1B4.N13  NC_FPGA_PB9F_DNU'0001111000'
!  245 245     U1B4.N13  NC_FPGA_PB9F_DNU'LLLHHHHLLL' ! PO Monitor
!  281 281     U1B4.N8   TP_PLD_LEFT<23> '1000111100'
!  281 281     U1B4.N8   TP_PLD_LEFT<23> 'HLLLHHHHLL' ! PO Monitor
!  295 295     U1B4.N6   TP_PLD_LEFT<21> '1000011101'
!  295 295     U1B4.N6   TP_PLD_LEFT<21> 'HLLLLHHHLH' ! PO Monitor
!  299 299     U1B4.N5   TP_CPLD_REV0    '0010010101'
!  299 299     U1B4.N5   TP_CPLD_REV0    'LLHLLHLHLH' ! PO Monitor
!  315 315     U1B4.P3   TP_PLD_LEFT<20> '0111110000'
!  315 315     U1B4.P3   TP_PLD_LEFT<20> 'LHHHHHLLLL' ! PO Monitor  

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