All,
Recently, I have a BoudaryScan case on Intel@SCH platform. I came up with the problem it can't enter into scan mode.
The boundary scan chain is a daisy chain, which link cpu and dock, all the tap signals and compliance signals are ok. But all the tests, even the disable test can't enter into scan mode. I break out the chain and test them seperately, cpu, the front side of chain can work sometimes, but not stable; meanwhile, the dock(intel@sch) always can't enter into the scan mode. I just heard the Agilent UGM have metioned that, some intel platform need addtion signal sequence for initialization, then can enter into the scan mode. Anybody here can share the new knowledge with me ? Any references for this application?
Many Thanks,
bin
Recently, I have a BoudaryScan case on Intel@SCH platform. I came up with the problem it can't enter into scan mode.
The boundary scan chain is a daisy chain, which link cpu and dock, all the tap signals and compliance signals are ok. But all the tests, even the disable test can't enter into scan mode. I break out the chain and test them seperately, cpu, the front side of chain can work sometimes, but not stable; meanwhile, the dock(intel@sch) always can't enter into the scan mode. I just heard the Agilent UGM have metioned that, some intel platform need addtion signal sequence for initialization, then can enter into the scan mode. Anybody here can share the new knowledge with me ? Any references for this application?
Many Thanks,
bin
Since the dock(Intel@sch) is not entering Bscan mode at all, you probably cannot get them working in a chain.
I have worked on a few Intel Chipset recently, and they do required initialization pattern for chipset to enter Bscan mode. Unlike the usual static compliance pins declared in BSDL (which you only need to drive them to a defined state), you will actually need to toggle the compliance pins according to certain pattern before it enter Bscan mode.
So far, i do see the description of the compliance pattern (that we need to toggle) at the end of the BSDL file.
Please check the BSDL file that you have for that info. (provided the chipset that you are working on does need a initialization sequence).
Hope this helps you in your debug.
Regards,
BC