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Defining cal kit for on-wafer TRL

Question asked by mattski on Sep 15, 2010
Latest reply on Sep 23, 2010 by Dr_joel
I am using an E8361A to do a two-port on-wafer TRL calibration from about 4-30GHz.  I am using 2.4mm cables to Cascade Infinity 100um probes.  My on-wafer standards consist of GSG pads with signal line tapering to the transmission line width (5um) with a dual open, dual short, and a through of 15um length.  My line is 2mm.  I used the short circuit as my reflect standard, and selected to use the reflect standard to define the reference plane.  For this particular measurement though it would also be fine to use the center of the Thru.

When one of my friends demonstrated the TRL calibration to me he told me when I set up the open and short cal standards in the VNA to put in the C0 or L0 field the open capacitance or short inductance which is specified by Cascade for my probes.  I am not sure though, because my open and short are not at the probe tip but on chip, so my probe's parasitics should be lumped into the entire error network which preceeds the calibration plane.

So I did my calibration two ways, specifying the probe short inductance 3.3pH, and again leaving the short L0=0.  My data looks reasonable to me with both ways of calibrating.  Should I specify these parasitics for on-wafer TRL or leave them at 0?

Plotted below is the result of measuring phase of gamma_reflect for the short circuit.  The red trace is when I specified L0=3.3pH, black when L0=0.
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