AnsweredAssumed Answered

How to Simulate Even Mode Impedance in Schematic View on ADS

Question asked by YouCannotEscapeThermodynamics on Dec 9, 2020
Latest reply on Dec 11, 2020 by bafisher

Hi,

I have a question regarding multiple excitation on schematic view. During the design phase (e.g. HPA, phase shifter etc), I would use a setup (shown below) to excite the circuit in common mode and check each even mode impedance at a different port.

For IP related reasons, I cannot share the actual layout but this should prove sufficient to explain it. This would be the most basic output combiner layout. VCVS (voltage controlled voltage source) has input impedance of 1e100 (not loading TermG1) and an output impedance of zero with gain of 1. I do this type of analysis to check the even mode impedance, phase difference between ports and if necessary, introduce layout assymetry to correct the phase of the RF path.

 

What I have observed is for structures in the picture above, the analysis works fine. However, for more complex structures, such as active device manifolds (simulated by EM), gamma seen by TermG1 doesn't make much sense, in fact it becomes greater than 1 at certain frequencies, even though the circuit is completely passive (heavily implying that TermG1 itself is loading some of the VCVS components when it really should not as the phase difference should be minuscule). I have not encountered this behaviour previously, so any tip on this is highly appreciated.

 

Please feel free to share your own approach to simulating even mode impedances as well.

 

Thanks.

Outcomes