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Static frequency divider by 2

Question asked by zai_kun_93 on Jul 31, 2020

Hello,

I am trying to design a static frequency divider using TAHB analysis. I tried to emulate the design guide example as mentioned in the design guide "DivBy 2 using BJT Sinusoidal Source using TAHB". 

This design example is given for a clock frequency of 1GHz.

My current requirement is to design for higher frequencies in the D band -mmWave range(110GHz). But Iam having trouble to setup a testbench for this operating frequency. As far my topology is concerned it is the same latch implemented as in the design guide example (Dlatch with an EmiiterFollower ).

 

Please guide how to setup a test bench that will help me to achieve simulation for this frequency.

and also let me know how does the settings of the HBNoise Controller change and Options would change as per the frequency.

 

My simulation erros for increeasing the frequency is as below:

Error detected by hpeesofsim during HB analysis `HB'.

    Convergence hints:TAHB_setupCircuit_schematic

    o Select the direct solver.

    o Check the circuit/devices around the nodes in solver convergence summary.

    o Check the circuit/devices around the nodes in solver convergence summary.

 

 

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