Transistors (active die) are embedded in ever more sophisticated packages.
These packages (eg QFN-type) are then soldered on top of a PCB.
We use FEM simulations to account for all impedance transformations due to the passive connections.
The most important is the added source-inductance because of the via-farm in the PCB underneath the QFN and in the embedded ground coin of the QFN package itself.
Usually the FEM simulated EM effects of the packaging environment and the active model of the transistor are combined in a schematic and then used together for Harmonic Balancing or S-parameter simulations.
We can understand that the S-parameters resulting from the FEM simulation account for the added Ground Inductance effect. However, there is a myriad of possibilities to generate look-alike components with pins and to connect the active model to one-another. What are the best practices here?
Under the FEM examples that come with ADS, there is an example workspace QFN_Designer_wrk.
In this example, the QFN package does not contain an active transistor, but a simple uStrip line. This makes a comparison with a simulation of the full layout easy and it allows us to ponder about the pinning and the porting.
The uStrip-line is simulated in a separate, simple 2-port Momentum Simulation. Then, the rest of the problem (with 2 wirebonds) is simulated in FEM. In this latter setup, 2 single-ended ports are defined to global ground at the edges of the problem, and additionally, two internal differential ports are configured inside the QFN package and the line removed. See fig Keysight_embedding.png.
Note the double pins for the Differential ports in the QFN-lookalike layout. Note how the explicit gnd pin of the uStrip look-alike symbol of the uStrip line was added and how that pin is connected to the reference pins of both differential ports.
I ran these simulations and compared it with the full-wave 2-port simulation and noticed an important discrepancy.
That's when I started playing with the ports. This is what I did:
I undid the differential definition of the internal ports in the QFN-section and just considered each pin as a single-ended port, each referenced to the global gnd. Then the S-parameters aligned. This excellent reference: https://muehlhaus.com/support/ads-application-notes/em_line_ground explains how differential ports only let the differential current circulate, while the 6-port single-ended approach is the more universal definition.
I removed the two reference pins from the QFN-section all together and hence simulate the QFN section with only 4 SE-ports. Thus, the layout lookalike has 4 pins and I connect them like below. S-parameters lined up very well. Note how the explicit gnd-pin of the uStrip lookalike symbol is connected to global ground! This may throw off many, because if the uStrip were a transistor, they don't want to connect the gnd of the transistor to global ground, the entire idea to study the effect of the source-inductance is that the gnd potential of the transistor gets offset from the global gnd!
Well, that is not how S-parameters work, as argued in the mentioned reference,
The underlying reason is the concept of Port Regularity, as discussed here. Since S-parameters don't express the voltage drop between the references of the ports, you might as well consider them floating relative to one-another and therefore, there is nothing wrong with hanging all ports to global ground. The effect of Ls will be accounted for though, since the voltage in port 3, presented by that internal port to the active device, will be a reduced version of the input voltage. I tried this by replacing the uStrip by an active transistor.
I kept the differential definition of the ports in the QFN-section and next simulated the uStrip section as a differential problem: removed the infinite ground and mapped a cond-layer as the gnd. At each end of the uStrip, I added a pin on that layer and defined those as the minus - sign of the ports at each respective end of the uStrip. Thus, the layout-lookalike has 2 pins on each end of the line. See fig. Keysight_embedding_Diff.png. Here too, the S-parameters align very well.
From my understanding, according to the mentioned reference, the approach in Original Example should yield correct S-parameters because even if you connect the references of both differential ports to the same potential, the differential current will still flow: The 2-port model (result) with differential ports is “immune” to non-differential currents, and all current that flows into the signal conductor will return through the return path, no matter what else we try at schematic level.
So, why is it that the S-parameters correlate poorly? I admit that this 4-port problem is not exactly the same as the situation in the reference, but I am trying to extrapolate my understanding of it to this QFN problem.
It seems like you have to connect SE-ports with SE-ports and Differential ports to Differential ports in order to get correct S-parameters.
What am I still not understanding here?
Thanks for any help/discussion.