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How to add pads/pins/names to GDSII layout for SIPro simulation?

Question asked by Sjoerd Op 't Land on Feb 19, 2020
Latest reply on Feb 25, 2020 by HERMANW

Dear all,

 

I am trying to perform SIPro simulations on a redistribution layer. This is essentially a single layer TSV to BGA pad fanout, etched on the bottom of a silicon chip. I will try to illustrate some things with images, but to protect customer IP, I need to be selective. Hopefully the explanations are sufficient.

 

The layout is imported from a GDSII file, with a top-level hierarchy as shown below. On the top level, there is an instance of BGA_PADS, which contains a 10x10 array of PADs (circular polygons). On the top level, there also is an array of TSVs (circular polygons). Finally, there are polygons which are the fan-out traces. The BGA pads, TSVs and traces all exist on one common copper layer (the pads and TSV also exist on other layers, but I ignore those layers for now). There are no net names or ports defined in the GDSII import.

 

When importing this layout in SIPro/PIpro, the following happens (see below). The traces are correctly imported, but the BGA pads and vias are not. Moreover, the BGA_PADS shows up as a single instance I_0 without pin. The TSV shows up as an array of instances, but also without pins.

 

My question is threefold, but probably they are interrelated.

  1. How do I include the pads in the SI simulation? One solution that worked was to 'Flatten' the components in layout: the compact 10x10 array is transformed in a list of 300 polygons. For SI simulation, this is good, but what if I need to change the pad size one day? Is there really no other solution?
  2. How do I add pins to the SI simulation? One solution that kind of worked, was to add a port to the TSV primitive, but this yielded a list of ports with names like I_1[0,7]_P1 and also seemed to connect to the same net. Probably, this is not the right way to do it.
  3. How do I add signal names to the SI simulation? One solution that kind of worked, was to add net names to the trace polygons, but probably there is a proper way to do this. Ideally, I would like assign signal names to the TSVs, because in the actual design, this is fixed (whereas the BGA pinning is still open for changes). The interconnects and BGA pads should then deduce their nets from connectivity with the TSVs.

 

Thanks in advance for your time and attention,

Sjoerd Op 't Land

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