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Changing seed for $random in Verilog-A has no effect

Question asked by rkk on May 2, 2019

Hello,

 

I have written a basic verilog-a file that I am using in an ADS transient simulation to generate a random voltage. It works as expected except for when I change the seed the output from one seed to the next remains the same. I have even manually entered the seed rather than using a parameter but this has no effect. Why is the output of the simulation not changing when I change the seed? Below is the code,

 

`include "disciplines.vams"
`include "constants.vams"

module my_random_number(p, n);
   inout p,n;
   voltage p,n;

 

   parameter integer nSeed = 12345;

 

   analog begin
      V(p) <+ V(n) + $random(nSeed);
   end

endmodule

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