Substrate editor allows to setup plated, plugged vias but the EM simulator says that it currently doesn't implement plated vias and plating will be ignored. Has anyone seen this? Is there something I need to set in the EM setup?
Plated vias are only supported by PiPro; see this info from the documentation:
Svensson/Djordjevic dielectric model
Surface impedance conductor model incl. skin effect (sheet/thick)
Field modeling of conductor (Meshed interior)
Conductor roughness model (surface top/bottom)
Conductor roughness model (via sides)
Thanks for the response. Even though plating is not supported, the vias are conducting I assume. Otherwise, EM simulation would be incorrect on a substrate with more than one layer. So what is set for the via wall - perfect conductor, copper, what thickness if copper?
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