I am having a problem in simulating Load Pull simulation for a BJT transistor. I have fixed the bias point of the transistor for class AB mode with resistor divider network. I want to modify the loadpull instrument of the inbuilt load pull design kit of ADS 2017. I have set that simulation setup for available power sweep and I modified the load pull instrument with the proper resistor biasing but the transistor is showing very less PAE and the optimum input impedance is having negative real part. Can you please suggest any solution for this problem?