I am making a simulation of a 3-wire SPI serial channel (SCLK, MISO, MOSI) at 50MHz through a PCB, connected to a DUT, which is modelled through a SPICE model. I have ADS 2017.
I used the ChannelSimulation, with a TX, and a xTlk in order to simulate the MOSI, and the SCLK channels.
I am interested in the signal quality (eye diagram) of the MOSI at the SPICE model of my DUT in the PCB.
I was able to perform the simulation, however I have a problem regarding the clock.
I set the TX component to 50Mbps, however the xTlk cannot be set to send "01" with a speed of 100Mbps required to generate the "noise" clock.
How can I generate the clock signal without to go in a transient modelling/using the VtPulseDT component?
Thanks for the help.