We have successfully built LRL/TRL calibration kits for SMPM interface per MIL-STD-348 (.069”/1.75mm airline) . This kit consists of the following: short, thru, and a 3 different lengths of airlines. With this LRL kit, we were able to get good results up to 67 GHz when we assumed zero for the L0, L1, L2, L3 coefficients for the short on the Agilent 8361C VNA. **However, we are now attempting to build a SOLT calibration kit for SMP interface per MIL-STD-348. It appears that assuming zero for the L and C coefficients will not be sufficient for a good SOLT short open load thru calibration, so we are trying to figure out what the proper method of deriving/calculating L and C coefficients would be.** We have looked at several papers addressing calibration methods, but each one seems to do some “hand-waving” and leave out essential details on the method of deriving L and C coefficients for the open and short. Is there any document that clearly lays out the steps necessary to derive L and C coefficients that are sufficiently accurate to work for an SOL 1-port calibration? Any guidance/direction would be highly appreciated.

I wrote about this exact issue in Chapter 9 of my book ( http://www.wiley.com/WileyCDA/WileyTitle/productCd-1119979552.html ). The particular case was creating and evaluating PCB standards, but the methods are almost the same. Basic idea is:

Calibrate in a good type (3.5 mm). Use a high quality adapter or cable to connect to your test plane (which has your connector type). Use a short/open to get an idea of the proper reference plane. Then use gating to remove the effects of the 3.5 mm to adapter (or cable ) mismatch, or more simply, use AutoPortExtend to set the reference plane. Connect the short (I guess for this case, you just need the proper offset). For frequencies below 20 GHz, you can likely leave the L values to zero just fine. Then connect the open (it's best to use a shielded open so it does not radiate) and evaluate it's offset delay from the short, and get the phase curve. You may find the open is shorter (in distance) than the short, if you don't have an open pin extension). Use the phase curve to map to a 3rd order polynomial and get the coefficient from that.

Then evaluate the load as it appears at the reference plane, and look for the excess inductance (my experience is the load is almost always inductive, although I have seen some on-wafer standards that are in-fact capacitive). Compute the offset delay at 500 ohms to get the equivalent inductance.

Lots more details in chapter 9.