Hi guys !
I'm new on this forum. I found it doing research on Internet. I am working now for a few time with ADS and I am currently facing a quite strange problem.
1) RF signal Layer(TOP)
----Dielectric Layer
2) Analog Ground Plane
----Dielectric Layer
3) Supply plane
----Dielectric Layer
4) Bottom Layer(Bottom)
I have a 4-layer PCB and vias through all the planes. The thing is that for example if I want to have a connection using a via between let's say the RF Layer and the Supply Layer normally using VIAFC I should have a clearance on the Analog Ground Layer because there is no connection there.
But the problem is that it does the complete opposite . It puts a clearance on the layers that it is supposed to be connected and no clearance on the layer it is not supposed to be connected :-(
I have been struggling for this problem for hours and I can't find any solutions to it. I just don't understand why it does this error .... Could someone help me please ?
On the image below, the green plane is the supply plane and the red one is the analog ground, as you can see the VIAFC goes from the RF Layer to the Analog Ground but the clearance is not on the Supply Plane but on the Analog Ground Plane :s
Thank you all and I wish a nice morning/evening
The VIAFC component documentation does not say anything about clearance. You might want to use components from the TLines - Multilayer library, like MLVIAHOLE, MLVIAPAD, MLCLE (a via clearance component) If these do not work out, please contact your local Technical Support office for assistance.