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Verilog-AMS ADS bug or missing support?

Question asked by IvNesh49 on Sep 1, 2016
Latest reply on Sep 1, 2016 by bafisher

Hey folks,


I am trying to dynamically generate modules inside a verilog-AMS module.


However, ADS give out a "syntax error" at the for-loop-statement.


Is it because the for loop is not supported?


The example source is taken from the official manual (


module rcline (n1, n2);
inout n1, n2;
electrical [0:N] n;
electrical n1, n2, gnd;
ground gnd;
parameter integer N = 10 from (0:inf);
parameter Cap = 1p, Res = 1k;
localparam Csec = Cap/N, Rsec = Res/(2*N);
genvar i;
for (i=0; i <10; i=i+1) begin : section
electrical n_int;
resistor #(.r(Rsec)) R1(n[i], n_int);
resistor #(.r(Rsec)) R2(n_int, n[i+1]);
I(n_int, gnd) <+ Csec * ddt(V(n_int));
analog begin
V(n1, n[0]) <+ 0.0;
V(n2, n[N]) <+ 0.0;


Kind Regards