Hello,

I would like to ask what is the ADC resolution (number of bits) of an 8510 system and a PNA system? What are the quantization steps of the calibrated VNA? Do they depend on the source power setting and the maximum input power? Are the ADCs in the 8510 and the PNA linear or logarithmic?

I somehow feel that quantization errors are not of great importance for VNA measurements but I really like to know how big they are actually .

Best Regards,

Johannes

I would like to ask what is the ADC resolution (number of bits) of an 8510 system and a PNA system? What are the quantization steps of the calibrated VNA? Do they depend on the source power setting and the maximum input power? Are the ADCs in the 8510 and the PNA linear or logarithmic?

I somehow feel that quantization errors are not of great importance for VNA measurements but I really like to know how big they are actually .

Best Regards,

Johannes

In the 8510, I'm not sure. I'll leave it to someone else to answer, but I would guess 14 bits. The 8510 had synchronous detectors, so that the signal was converted to I and Q outputs (real and imaginary) and these DC signals were digitized. Everything was done in linear voltage, and the log applied mathematically.

The question is not easy to answer for the PNA, because of the ADC technnology used. There were different ADCs used in different versions, typically 14 or 15 effective bits, but earlier versions used "step gain" in front of the ADC so that the bits are extended by the step gain value. During measurment, the size of the signal is determined, and step gain is added if the signal is small so that the ADC range is extended. In the newer versions, an ADC dithering signal is added, which adds noise into the ADC, where the noise is shaped to be only at higher frequencies, then the digital filter removes the noise and leaves only the signal. In this way, quantization errors are essentially eliminated (the noise "smears" the quantization). These ADCs have about 16 effective bits, but we refer instead to the S/N range, which is about 133 dB in a 10 Hz BW. The dithering eliminates quantization errors, so the noise floor is limited only by averaging and effective BW, both of which can be extended. These systems are highly oversampled, and complex digital filtering techniques can be used for a wide range of signal processing functions. For example, in the PNA-X, the final down conversion is done completely digitally, and the final IF is set by an NCO (numberically controlled oscillator) in the DSP, so it is really like a software defined IF.

For most systems, the PNA max power is about +13-+15 dBm at the test port, which will cause the ADC to limit, but this can be extended by adding receiver attenuation, and at higher frequency, conversion loss roll-off of the first IF extends the ADC clip level. In addition, we add IF step gain per band to optimize the the IF response to create a more conisitent IF level at the ADC input. So, normal rules don't apply for figuring out digitization errors as we apply a lot of adaptive compensations to the results. Your best bet for understanding these effects is to use the VNA uncertainty calculator which includes noise floor and linearity effeects.