I'm doing a Ph.D in MMIC design for uW frequencies and I'm new to ADS and EMPro, though I have experience with MWOffice and CST, so I'm familiar with EM simulations.
I'm trying to export an ADS PA MMIC design (with a proprietary PDK) to EMPRo, and simulate it with the FEM and FDTD engines. For that purpose, instead of exporting the whole project I just export a via and a microstrip line, using the export button in the EM Setup(FEM). When I check the exported geometry in EMPro, I see that the various substrate layers (dielectrics, resistance sheets, metals...) of my PDK are correctly stacked up, but there where two or more solids coexist, neither material volume is voided to place any other solids E.g.:
Vertical via metal through several substrate layers: Substrate layers remain continuous, with no "punching holes" where via should exist, in a given location, both via solid and dielectric layers solids coexist.
My first question is whether I have to manually fix this, or if there is any mechanism (kind of material precedence setting, like in the PDK) to overcome this type of issues. This is also applicable to the case when an upper air layer is placed above a circuit. Do I have tofirst define a PEC sheet in the dielectric-air interface and then extrude it(Hoping the extrusion process voids "air volume" to accomodate the metallic extrusion)?
And secondly, Do waveguide ports (modal or nodal) have to be located in the boundaries of the simulation box? Can they be located inside the simulation domain?(E.g.: Long microstrip line with one WGport located in a boundary, and the other WGport to be placed in different inner positions along the microstrip line to measure it instead of having to modelate a shorter microstrip reducing the strip, ground plane and substrate lengths)
I have many more questions but sure this is enough for now.
Thanks in advance, regards.