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EM-cosmulation vs. schematic results of the pcb board

Question asked by jeff0283 on Dec 16, 2015
Latest reply on Dec 26, 2015 by volker_muehlhaus

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Hi, I am designing a power amplifier on the pcb board.
I want to see the impedance of the bias part(RF choke to the DC input terminal).
I've compared the results of schematic and em-cosimulation,
Layout.png
schematic.png

But the two results are quite different.(red is for em-cosimulation and blue is for schematic)
result2.png

You can see there is a knot on the red curve, and I am wondering if my em setup is right...
Here is the result of em simulation result(only for layout not em-cosimulation),and it looks strange...
result.png

Does anyone have any idea??
Thanks~

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Layout.png48.1 KB
schematic.png41.9 KB
result.png63.5 KB
result2.png64.6 KB

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volker_muehlhaus Dec 17, 2015 5:05 AM

In a grounded CPW, you need to connect the top ground plane to the bottom ground plane. These vias only exist near the thru line, but not in the vertical path. Current at C40 can only flow to the top ground, with no direct path (via) to the bottom ground. The short at the end of the line connects only to the bottom ground, but leaves the top grounds floating.

Check results after placing vias that connect the different grounds.

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novia.PNG51.7 KB

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jeff0283 @ volker_muehlhaus on Dec 17, 2015 7:37 PM

I have tried two ways to modify my layout.
The first way is to add vias along the bias transmission line, and the second way is to just add one via at the position of the ground pin of the bypass capacitor.
modified_layout.png
modified_layout2.png

Here is the em simulation result,where red curve is for many vias and blue curve is for one via.
But they look different.
modified_result1.png

Here is the em co-simulation result. They look the same,which overlap with each other, and the knot disappears, which look more accurate than the original result.
modified_result2.png

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jeff0283 @ jeff0283 on Dec 17, 2015 11:19 PM

Sorry,there is something wrong.

For the case of one via beside the ground pin of bypass capacitor, the result of em co-simulation still has a knot which looks strange
So only for the case of many vias along the bias line, the result is a smooth curve.

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jeff0283 @ volker_muehlhaus on Dec 26, 2015 6:06 AM

Hi volk:

Thank you for giving the advice. After I added the holes, the result became smooth and accurate.
But actually my real pcb board doesn't have these holes added afterwards, maybe the original result matches the measurement result???

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volker_muehlhaus @ jeff0283 on Dec 26, 2015 1:00 PM

> {quote:title=jeff0283 wrote:}{quote}
> But actually my real pcb board doesn't have these holes added afterwards, maybe the original result matches the measurement result???

If the missing holes cause trouble in simulation, you should see the same effect in measurement, if the load impedance at the port is the same.

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5 Replies

volker_muehlhaus Dec 17, 2015 5:05 AM
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Correct Answer
In a grounded CPW, you need to connect the top ground plane to the bottom ground plane. These vias only exist near the thru line, but not in the vertical path. Current at C40 can only flow to the top ground, with no direct path (via) to the bottom ground. The short at the end of the line connects only to the bottom ground, but leaves the top grounds floating.

Check results after placing vias that connect the different grounds.
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- novia.PNG51.7 KB
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- jeff0283 @ volker_muehlhaus on Dec 17, 2015 7:37 PM
  Mark Correct
  Correct Answer
  I have tried two ways to modify my layout.
  The first way is to add vias along the bias transmission line, and the second way is to just add one via at the position of the ground pin of the bypass capacitor.
  modified_layout.png
  modified_layout2.png
  
  Here is the em simulation result,where red curve is for many vias and blue curve is for one via.
  But they look different.
  modified_result1.png
  
  Here is the em co-simulation result. They look the same,which overlap with each other, and the knot disappears, which look more accurate than the original result.
  modified_result2.png
  Attachments
  - modified_layout.png43.8 KB
  - modified_layout2.png48.0 KB
  - modified_result1.png63.9 KB
  - modified_result2.png51.8 KB
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  - jeff0283 @ jeff0283 on Dec 17, 2015 11:19 PM
    Mark Correct
    Correct Answer
    Sorry,there is something wrong.
    
    For the case of one via beside the ground pin of bypass capacitor, the result of em co-simulation still has a knot which looks strange
    So only for the case of many vias along the bias line, the result is a smooth curve.
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- jeff0283 @ volker_muehlhaus on Dec 26, 2015 6:06 AM
  Mark Correct
  Correct Answer
  Hi volk:
  
  Thank you for giving the advice. After I added the holes, the result became smooth and accurate.
  But actually my real pcb board doesn't have these holes added afterwards, maybe the original result matches the measurement result???
  Like • Show 0 Likes0
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  - volker_muehlhaus @ jeff0283 on Dec 26, 2015 1:00 PM
    Mark Correct
    Correct Answer
    > {quote:title=jeff0283 wrote:}{quote}
    > But actually my real pcb board doesn't have these holes added afterwards, maybe the original result matches the measurement result???
    
    If the missing holes cause trouble in simulation, you should see the same effect in measurement, if the load impedance at the port is the same.
    Like • Show 0 Likes0
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EM-cosmulation vs. schematic results of the pcb board

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