Hello,
I have a 16802 Logic Analyzer and I want to measure the time delay in an asynchronous communication between a PC and other devices. This communication uses the HDLC protocol at a baudrate of 921.6 kbps. The issue is that the delays are usually higher than 300 ms, therefore the internal memory is not large enough to save all the samples. I wonder if there is any way to configure the logic analyzer so that it saves only the frames we want and it counts the time between frames without saving the information. I have tried to program an advanced trigger, but it seems that only fills the memory from a single point.
Another question is the possibility of synchronizing the signal with the LA. Is it really possible? The maximum sampling resolution is 10 ns, so I cannot sample at that baudrate, and I do not know what to do to avoid bit errors.
Thanks for your help!
Regards,
Roberto Cuerdo
I have a 16802 Logic Analyzer and I want to measure the time delay in an asynchronous communication between a PC and other devices. This communication uses the HDLC protocol at a baudrate of 921.6 kbps. The issue is that the delays are usually higher than 300 ms, therefore the internal memory is not large enough to save all the samples. I wonder if there is any way to configure the logic analyzer so that it saves only the frames we want and it counts the time between frames without saving the information. I have tried to program an advanced trigger, but it seems that only fills the memory from a single point.
Another question is the possibility of synchronizing the signal with the LA. Is it really possible? The maximum sampling resolution is 10 ns, so I cannot sample at that baudrate, and I do not know what to do to avoid bit errors.
Thanks for your help!
Regards,
Roberto Cuerdo
Also, you may want to set your trigger position to something like 1%.
Al
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