AnsweredAssumed Answered

re: Layout vs schematic simulation results

Question asked by lem on Jul 10, 2015
Latest reply on Jul 11, 2015 by lem

I designed a LCL circuit for testing purposes using 2 micro strips and a chip cappacitor. I run the S parameter on it and i get the expected results but when i generate/update the layout and run the EM the results are totally off. I checked the FR-4 substrate and i changed the capacitor type , added solder pads ,frequency range etc. Compared the two S11 parameters the circuit simulation is -20dB at the desired frequency and -001dB simulated with EM.
I really don't understand why this is happening.

Can you please advise 

Thank You
PS: I also designed a LPF and all worked out-this schematic is in the same project and uses the same defined substrate