Dear Sir/Madam,

I am trying to simulate a communication between transmitter and receiver, using the frequency of 920 MHz. While I am generating a carrier using eather CW Source or a Multi Source I do not have any problems and I can see the carrier at the receiver part easily.

Now, I would like to increase the complexity of the system and create an OOK modulated signal at the Tx part, that consists of a few bits of data (lets say 36 bits). The power of the transmitted signal has to be, e.g. 20 dBm. I can create the sequence easily by using a VBITSTR model or a MOD_VBIT model.

In the first case, using VBITSTR model I am creating just a data pattern (a stream if bits) and it is not modulated (does not have a carrier), Fig. 1.

In the second case I have a carrier and the pattern (a sequence of bits), but it is not an OOK modulated signal and also I got an error "Transcient Analysis convergence failutre", while connecting it to other blocs (splitters, filters, diplexers, etc.).

So, how can I simulate an OOK modulated signal of a certain BIT pattern using the Genesys?

Thanks in advance

PS I have checked all the examples in Modulation folder, but I still did not find an answer for me.

Edited by: Konstantin on Oct 28, 2014 8:51 AM

I am trying to simulate a communication between transmitter and receiver, using the frequency of 920 MHz. While I am generating a carrier using eather CW Source or a Multi Source I do not have any problems and I can see the carrier at the receiver part easily.

Now, I would like to increase the complexity of the system and create an OOK modulated signal at the Tx part, that consists of a few bits of data (lets say 36 bits). The power of the transmitted signal has to be, e.g. 20 dBm. I can create the sequence easily by using a VBITSTR model or a MOD_VBIT model.

In the first case, using VBITSTR model I am creating just a data pattern (a stream if bits) and it is not modulated (does not have a carrier), Fig. 1.

In the second case I have a carrier and the pattern (a sequence of bits), but it is not an OOK modulated signal and also I got an error "Transcient Analysis convergence failutre", while connecting it to other blocs (splitters, filters, diplexers, etc.).

So, how can I simulate an OOK modulated signal of a certain BIT pattern using the Genesys?

Thanks in advance

PS I have checked all the examples in Modulation folder, but I still did not find an answer for me.

Edited by: Konstantin on Oct 28, 2014 8:51 AM