I have a Verilog-A model of a device. But I have problems with DC convergence.
I'd like to try setting an initial guess for some node voltages within the Verilog-A model.
(As I could using the NodeSet object in an ADS schematic).
I know that if a branch is defined with the idt() function I scan specify an initial condition. But this locks the branch parameter for DC simulation, rather than just setting an initial guess.
How can I get the equivalent of a NodeSet for an internal node in a Verilog-A model?
Also, if there is any way to see intermediate steps in the DC analysis, that could help me diagnose my convergence problem.
Thanks,
Matt
I'd like to try setting an initial guess for some node voltages within the Verilog-A model.
(As I could using the NodeSet object in an ADS schematic).
I know that if a branch is defined with the idt() function I scan specify an initial condition. But this locks the branch parameter for DC simulation, rather than just setting an initial guess.
How can I get the equivalent of a NodeSet for an internal node in a Verilog-A model?
Also, if there is any way to see intermediate steps in the DC analysis, that could help me diagnose my convergence problem.
Thanks,
Matt