I'm debugging a PCIe link training problem with the U4301A analyzer and the version 05.60.000 of the logic and protocol analyzer (LPA) software.
If I run one training sequense I get up(endpoint tx) and down(root complex tx) trafic as expected, but if I re run the training sequence until i fails I only get Down trafic on the werry end. in the LTSSM i se the up state maching going trough the right states(exept for the failing run) so there mush have been down traffic. But all I see on down is polling state at the verry end.
Any ideas? I use the stop butten as trigger.
If I run one training sequense I get up(endpoint tx) and down(root complex tx) trafic as expected, but if I re run the training sequence until i fails I only get Down trafic on the werry end. in the LTSSM i se the up state maching going trough the right states(exept for the failing run) so there mush have been down traffic. But all I see on down is polling state at the verry end.
Any ideas? I use the stop butten as trigger.
What speed are you running?
Are you using the LTSSM Viewer, or are you looking at the LTSSM some other way? How do you know what's happening on the link?
Do you reset in between running the training sequences?
Which direction, upstream or downstream is missing traffic?
What happens when you use TS1 or TS2 as a trigger?
Have you looked at the link with an oscilloscope? Do the eyes look good? What about jitter? When a system can't link reliably it is quite often an electrical issue.
Al
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