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PCIe analyzer not storing traffic from both directions

Question asked by torr on Aug 26, 2013
Latest reply on Sep 2, 2013 by algoss
I'm debugging a PCIe link training problem with the U4301A analyzer and the version 05.60.000 of the logic and protocol analyzer (LPA) software.

If I run one training sequense I get up(endpoint tx) and down(root complex tx) trafic as expected, but if I re run the training sequence until i fails I only get Down trafic on the werry end. in the LTSSM i se the up state maching going trough the right states(exept for the failing run) so there mush have been down traffic.  But all I see on down is polling state at the verry end.

Any ideas? I use the stop butten as trigger.