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Ground reference for internal port_momentum

Question asked by Leyo on Mar 2, 2014
Latest reply on Jul 28, 2015 by jeff0283

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Hi,
This is regarding the ground reference for the internal and EDge ports in ADS momentum (Version used ADS2012 08).
Going through the following link and other documentation, would like to make sure that I am doing it correct.
http://muehlhaus.com/support/ads-application-notes/em_line_ground

Attached below are the substrate definition and layout==>

Read that the Edge port P1 and internal ports P4 P7 etc. will get implicit ground reference if there is "Infinite ground plane in the substrate definition"
How to do this in the substrate definition ?.
Is my substrate definition OK and take care of the infinite ground plane?
Do I need to select the option "Add Reference pin " in my case?
Also, in my PCB, I have shielding around 1 cm above the copper. I have defined it as cover in the substrate definition. Am I doing it correct?

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substare.PNG33.4 KB
Copper.PNG16.0 KB

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volker_muehlhaus Mar 2, 2014 11:54 PM
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You substrate has an infinite ground below (microstrip), at the bottom of the substrate. By default, all ports are referenced to that ground. This will work fine, and there is no need to define (-) reference pins.

From your picture, I do not understand what P1 represents? You have another thread open where that P1 is large, along the entire edge. What you do you want to model with such a wide port?
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- Leyo @ volker_muehlhaus on Mar 3, 2014 3:52 AM
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  Thanks about the ground plan explanation. Now it is clear.
  Regarding the the other thread that shows a long edge with an edge port, please see the below picture.
  This is the matching circuit for a LDMOS device. The LDMOS tab is connected to the copper as shown. Then I have a quarter wave transmission line for bias feed to the LDMOS. At quarter wave end, I have the RF capacitor that acts as RF short at my frequency. Vdd is also applied here.
  If I understood correctly the P1 port on this long edge is not valid, right. Please let me know how to handle this situation?
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  - Capture3.PNG57.4 KB
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  - volker_muehlhaus @ Leyo on Mar 3, 2014 8:41 AM
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    > {quote:title=Leyo wrote:}{quote}
    > If I understood correctly the P1 port on this long edge is not valid, right. Please let me know how to handle this situation?
    
    It makes no sense on the *long* edge. In the hardware, nothing is connected there.
    
    If your transistor is connected where you have drawn it, on the *short* edge at the end of the lambda/4 line, place port P1 there. It's that simple!
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    - Leyo @ volker_muehlhaus on May 4, 2016 12:19 AM
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      Thanks... to make it more clear..
      As per the definition of the edge port, the whole edge of this copper( The LDMOS tab and the section of quarter wave on this edge) will be excited by the port, irrespective of the location of this port on the edge?. But in real life, the current will be excited only under the tab area where the LDMOS tab is connected, right?. Please help me correct this confusion.
      
      In your earlier post (I am always using it as reference) Power Amplifier Matching network simulation in Momentum
      you have mentioned to use "Port width = Transistor width". In my situation, the long copper (Including the LDMOS tab and section of quarter wave) width is is not equal to terminal width. So I have to use a copper with width equals to terminal width and connect to the long copper bottom edge and use reference offset in the EM set up calibration.
      
      Edited by: Leyo on Mar 3, 2014 11:27 AM
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      - volker_muehlhaus @ Leyo on May 4, 2016 12:22 AM
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        > {quote:title=Leyo wrote:}{quote}
        > As per the definition of the edge port, the whole edge of this copper( The LDMOS tab and the section of quarter wave on this edge) will be excited by the port, irrespective of the location of this port on the edge?.
        
        Yes. With P1 on the left side, the port will be 15cm wide, over the entire edge. This is not what you want. Your transistor is not connected there, and it does not have a 15cm wide feedline.
        
        > But in real life, the current will be excited only under the tab area where the LDMOS tab is connected, right?
        
        Yes. In your real hardware, the current excitation is where the transitor feedline connects to the PCB line. This is at the end of the lambda/4 line near the transistor, with width = transistor feedline width.
        
        > In your earlier post (I am always using it as reference) Power Amplifier Matching network simulation in Momentum
        > you have mentioned to use "Port width = Transistor width". In my situation, the long copper (Including the LDMOS tab and section of quarter wave) width is is not equal to terminal width. So I have to use a copper with width equals to terminal width and connect to the long copper bottom edge and use reference offset in the EM set up calibration.
        
        Yes, you can do this, see attached screenshot. If placed on the narrow edge, the port current would be over the entire width of the edge. That is not accurate if the transistor feedline width is much smaller than the width of the edge. In your case, not a big problem, but you can make it more accurate by adding a short metal segment with the correct width. If this short segement is very short, you do not need de-embedding of the extra length.
        
        Another possibility is to use an area pin where your transistor feedline connects to the PCB line. This is described in the ADS online help, see screenshot.
        Attachments
        areapin.PNG134.1 KB
        port_short.PNG4.0 KB
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  - volker_muehlhaus @ Leyo on Mar 3, 2014 8:42 AM
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    It makes no sense on the *long* edge. In the hardware, nothing is connected there.
    If your transistor is connected where you have drawn it, on the *short* edge at the end of the lambda/4 line, place port P1 there. It's that simple!
    
    PS: This forum's software is confused again ... I'll try to post again.
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- Leyo @ volker_muehlhaus on Mar 3, 2014 3:53 AM
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  Thanks about the ground plan explanation. Now it is clear.
  Regarding the the other thread that shows a long edge with an edge port, please see the below picture.
  This is the matching circuit for a LDMOS device. The LDMOS tab is connected to the copper as shown. Then I have a quarter wave transmission line for bias feed to the LDMOS. At quarter wave end, I have the RF capacitor that acts as RF short at my frequency. Vdd is also applied here.
  If I understood correctly the P1 port on this long edge is not valid, right. Please let me know how to handle this situation?
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  - Capture3.PNG57.4 KB
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- Leyo @ volker_muehlhaus on Mar 3, 2014 3:53 AM
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  Thanks about the ground plan explanation. Now it is clear.
  Regarding the the other thread that shows a long edge with an edge port, please see the below picture.
  This is the matching circuit for a LDMOS device. The LDMOS tab is connected to the copper as shown. Then I have a quarter wave transmission line for bias feed to the LDMOS. At quarter wave end, I have the RF capacitor that acts as RF short at my frequency. Vdd is also applied here.
  If I understood correctly the P1 port on this long edge is not valid, right. Please let me know how to handle this situation?
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  - Capture3.PNG57.4 KB
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  - volker_muehlhaus @ Leyo on Mar 3, 2014 8:45 AM
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    Place P1 on the short edge, where ypu have drawn the transistor
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volker_muehlhaus Mar 3, 2014 8:48 AM
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Place P1 on the short edge, where you have drawn the transistor.

****, this forum's software/database is corrupt again, and it doesn't manage/show the answers as expected.
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volker_muehlhaus Mar 4, 2014 7:29 AM
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Hello again,

it seems that this wonderful forum software has lost my previous post, where I spend much time on your case. I'll try one more time, and see what happens ....

Of course, you should not place P1 on the long edge, where the port would be 15cm wide on the left side. You want the port on the bottom side, where the transistor is. Add a very short piece of metal, with the width as the transistor feedline, and attach the port there.

Alternative: you can create an area pin inside the metal polygon, as shown in the other screenshot. The steps are described in teh AFS help.
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- areapin.PNG134.1 KB
- port_short.PNG4.0 KB
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- Leyo @ volker_muehlhaus on Mar 4, 2014 6:42 PM
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  Thanks for the detailed reply...
  
  1. I think some of my explanation was not detailed enough. The transistor (Lead width is 6.5 cm) comes on the left side of the long 15 cm track. So the option of connecting the port at the lower narrow edge (as shown in your reply) is not valid.
  
  2. I had added an edge port (edgeport.png) as shown in the attached diagram. Is this OK, right.
  
  3. Also, I have Port P2 and P3 here. This is for connecting lumped components in the schematics. P2 is defined as an internal point port (I am selecting calibration as "None" for P2). Here the current is excited at a single point, right. P3 is defined as an area port. Current will be excited in this whole area surrounding P3 uniformly, right. So, in other words an internal point port (P2) can be interpreted as an area port with zero area.
  
  4. Please look at the attached Refoofset.png. Here I have added a feedline with width of 6.5 cm (Transistor lead width) and length of 3 cm. Port P1 is connected in the edge of this feedline. In the port set up, a reference offset of 3 cm is added. This will give the same result as in step 2 above, right.
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  - edgeport.PNG10.7 KB
  - Refoffset.PNG10.1 KB
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  - volker_muehlhaus @ Leyo on Mar 5, 2014 12:12 AM
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    > {quote:title=Leyo wrote:}{quote}
    > 1. I think some of my explanation was not detailed enough. The transistor (Lead width is 6.5 cm) comes on the left side of the long 15 cm track. So the option of connecting the port at the lower narrow edge (as shown in your reply) is not valid.
    
    Correct. I misunderstood your drawing.
    
    > 2. I had added an edge port (edgeport.png) as shown in the attached diagram. Is this OK, right.
    
    It is difficult to see what you have done in the "edgeport" screesnhot. I do not see the extra polygon. Does it stand out to the left side? Otherwise, it might get merged with the other metal. I would add the 6.5cm wide feed with a short length (maybe 2mm). See port_edge.png
    
    In the emSetup settings, switch OFF the "Simplify the layout" option on the Preprocessing tab. This is to avoid automatic changes to the layout that might change or our small polygon.
    
    > 3. Also, I have Port P2 and P3 here. This is for connecting lumped components in the schematics. P2 is defined as an internal point port (I am selecting calibration as "None" for P2). Here the current is excited at a single point, right. P3 is defined as an area port. Current will be excited in this whole area surrounding P3 uniformly, right.
    
    Correct. The area port gives you control over the area where the excitation is.
    
    > So, in other words an internal point port (P2) can be interpreted as an area port with zero area.
    
    Almost correct. Not zero, but small. The area of P2 excitation will depend on the mesh density around P2.
    
    > 4. Please look at the attached Refoofset.png. Here I have added a feedline with width of 6.5 cm (Transistor lead width) and length of 3 cm. Port P1 is connected in the edge of this feedline. In the port set up, a reference offset of 3 cm is added. This will give the same result as in step 2 above, right.
    
    Correct, if you set the reference shift in the P1 port options, to remove the extra length. In your screenshot, I do not see the ref shift. It should be visible in the layout view, see refshift.png
    Attachments
    refshift.PNG6.5 KB
    port_edge.PNG6.3 KB
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    - Leyo @ volker_muehlhaus on Mar 5, 2014 5:12 AM
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      Thanks... I am slowly getting there.
      
      1. Again there was a mistake in the dimensions I had mentioned. Everything should be in mm, not cm. The transistor terminal width is 6.5mm and the wider trace it is attaching to is 15mm.
      
      2. For the EDGE port, I used a polyline, not a polygon. You can see it is a blue line on which port P1 is attached. is this OK? (attached Edgeport_Polyline.png). Here no need of reference offset?
      
      3. If we use the ploygon with 2mm (defined as edge port) as you mentioned and don't use the reference offset, will there be error in the results. The length of the edge,(I mean the bottom side) is only 2.5mm? (Attached Edgeport_Polygon.png)
      
      4. With 2 mm polygon added as per above step and defined as edge port, it is ok to do the reference offset, right.
      
      5. I fixed the reference offset issue as you pointed out in the previous reply.
      Attachments
      edgeport_polyline.PNG10.7 KB
      edgeport_polygon.PNG7.2 KB
      Refoffset.PNG3.7 KB
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      - volker_muehlhaus @ Leyo on Mar 5, 2014 5:28 AM
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        > {quote:title=Leyo wrote:}{quote}
        > 2. For the EDGE port, I used a polyline, not a polygon. You can see it is a blue line on which port P1 is attached. is this OK? (attached Edgeport_Polyline.png). Here no need of reference offset?
        
        I don't think that Momentum will "understand" your polyline, and expect that your port will be over the entire edge. But you can try. From the Momentum currents in the 3D current viewer, you should be able to see where the P1 excitation is.
        
        > 3. If we use the ploygon with 2mm (defined as edge port) as you mentioned and don't use the reference offset, will there be error in the results. The length of the edge,(I mean the bottom side) is only 2.5mm? (Attached Edgeport_Polygon.png)
        
        The longer that extra line, the larger the error. If you make that extra polygon as large as you have drawn it, you will need to de-embed the extra length (port reference shift). My approach was to make that line *really* short, and then use no de-embedding.
        
        > 4. With 2 mm polygon added as per above step and defined as edge port, it is ok to do the reference offset, right.
        > 5. I fixed the reference offset issue as you pointed out in the previous reply.
        
        The polygon with port reference shift in your screenshot Refoffset.png looks good to me.
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        Leyo @ volker_muehlhaus on Mar 5, 2014 5:55 PM
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        Hi,
        In the attached workspace, I have added all these.
        
        1. cell ==> Edge_Port. Port P1 is placed on the EDGE of the copper and the simulation and current visualization are working fine.
        
        2. Cell2==>Polygon_Port. Port P1 is placed on the the added rectangle edge and reference offset applied. Simulation and current visualization are working fine. For some reason, I am not able to see much difference in the current visualization of step 1 and 2. In Step 2, current should be limited to the width of the added rectangle?
        
        3. Cell 3 ==>Polyline_Port. Trying to do the "EDGE PORT with Polyline". Drew the polyline on the left edge of the trace. Added port P1 and snapped to the trace( And polyline). Selected the polyline. From "Edit menu selected "EDGE/Area pin". Clicked "Select Pin" and selected Pin1 and apply. Is this the correct way to assign the edge/area pin?. Simulation is working fine (with the warning The port setup needed to be corrected: Calibration will not be used for port "P1" (pin "P1" is not on the edge between a conductive and a nonconductive region)., but getting the error in the current visualization "A point location for Pin P1 is required in the flow, but the pin has not been defined as a point"..... Not able to figure out.
        
        4. Cell 4 ==>Edgepin_Inside. I am trying to put the edge/area port pin slightly inside the copper with polyline (As explained in the above step). During simulation, getting the error message (A polyline shape for pin P1 could not be simplified to a single segment.Only single segment polyline pin shapes are supported.The pin shape needs to be corrected in the layout.)....Not able to figure out.
        
        Appreciate your help.
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        Layout_Learn_wrk.7zads137.1 KB
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        Leyo @ Leyo on Mar 6, 2014 7:46 AM
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        Hi,
        I figured out errors in items 3 and 4. It is   drawing mistakes from my side.
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        jeff0283 @ Leyo on Jul 18, 2015 9:43 AM
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        > {quote:title=Leyo wrote:}{quote}
        > Hi,
        > I figured out errors in items 3 and 4. It is   drawing mistakes from my side.
        Hi Leyo:
        How did you solve the warning message of 3.??I've had the same warning.
        
        My design is as the attachment design.png.
        I set P1 as the area port, choosing "TML" calibration,
        but encounter the same warning message:
        "The port setup needed to be corrected:
        Calibration will not be used for port "P1" (pin
        "P1" is not on the edge between a conductive and
        a nonconductive region)."
        The other ports(which are all area pins) have the same warning message.
        I don't know what this message mean??
        
        Edited by: jeff0283 on Jul 18, 2015 10:42 AM
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        design.png18.2 KB
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        gigan @ jeff0283 on Jul 23, 2015 3:58 AM
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        Hi jeff0283,
        
        did you solve the warning message of 3 problem? How?
        
        Please answer.
        
        ..........................................................
        
        ok .... It seems I solved it...
        
        Edited by: Gigan on Jul 23, 2015 4:57 AM
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        jeff0283 @ gigan on Jul 23, 2015 7:08 AM
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        Hi Gigan:
        How did you solved the calibration problem??
        I have no choice but to choose "None" calibration, but I don't know if it is right??
        
        Thanks~
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        volker_muehlhaus @ jeff0283 on Jul 27, 2015 11:32 AM
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        > {quote:title=jeff0283 wrote:}{quote}
        > How did you solve the warning message of 3.??I've had the same warning.
        
        The warning text is for information, and it tells you that calibration is not available for this port type. This is not an error, only warning that you set calibration where it is not available.
        
        > I set P1 as the area port, choosing "TML" calibration,
        > but encounter the same warning message:
        > "The port setup needed to be corrected:
        > Calibration will not be used for port "P1" (pin
        > "P1" is not on the edge between a conductive and
        > a nonconductive region)."
        > The other ports(which are all area pins) have the same warning message.
        > I don't know what this message mean??
        
        The message means what the text says: calibration is only possible for ports that are on the edge. Area ports can't be calibrated. But don't worry, that is not a problem and you will get useful results without calibration. To get rid of the warning, you can switch off calibration for this port.
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        jeff0283 @ volker_muehlhaus on Jul 28, 2015 2:29 AM
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        Hi volker_muehlhaus:
        
        Ok, I see.
        Thank you for reply.~
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        volker_muehlhaus @ Leyo on Mar 6, 2014 8:17 AM
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        > {quote:title=Leyo wrote:}{quote}
        > 1. cell ==> Edge_Port. Port P1 is placed on the EDGE of the copper and the simulation and current visualization are working fine.
        
        Yes, but the current is not what you want. The excitation is over the entire edge -> WRONG.
        
        To make the current flow more obvious, I moved P2 to the end of the line. Now you can see where the current is injected, it takes the shortest possible path from P1 to P2. And because the port is over the entire edge, it enters into the lambda/4 line at the wrong position. See attached picture current_edgeport.
        
        > 2. Cell2==>Polygon_Port. Port P1 is placed on the the added rectangle edge and reference offset applied. Simulation and current visualization are working fine. For some reason, I am not able to see much difference in the current visualization of step 1 and 2. In Step 2, current should be limited to the width of the added rectangle?
        
        With my modified position of P2, you can now see the difference. See attached picture current_addpolygon.
        
        > 3. Cell 3 ==>Polyline_Port. Trying to do the "EDGE PORT with Polyline". Drew the polyline on the left edge of the trace. Added port P1 and snapped to the trace( And polyline). Selected the polyline. From "Edit menu selected "EDGE/Area pin". Clicked "Select Pin" and selected Pin1 and apply. Is this the correct way to assign the edge/area pin?.
        
        This does "something", but I would have used a polygon (area) instead of a polyline (line). It seems that ADS is confused by using a line. If we do the same thing with a polygon (rectangle), it works and does not cause trouble in the current viewer. In the attached workspace, see model "areapin".
        
        > 4. Cell 4 ==>Edgepin_Inside. I am trying to put the edge/area port pin slightly inside the copper with polyline (As explained in the above step).
        
        Same mistake as in 3. Don't use a line, because line has zero area. Use a rectangle or polygon for area pins.
        
        My modified workspace is attached. Note that I moved P2 to have more visible currents.
        *Also note that I changed the mesh: switched Edge Mesh ON, switched Mesh Reduction OFF. You mesh looked much too coarse to me. We need a finer mesh so that current can flow in the physically correct locations.*
        Attachments
        currents_edgeport.PNG286.2 KB
        currents_addpolygon.PNG323.5 KB
        Layout_Learn_1900_wrk_volker.7zads918.3 KB
        currents_areapin.PNG303.0 KB
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        Leyo @ volker_muehlhaus on Mar 6, 2014 9:50 AM
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        Thanks for your help and time to explain this...Really helpful for us..
        I am going through your rely carefully to understand.
        One quick question ( I   am new to this visualization tool).
        In your plot, I could see "Red Big arrows" on the left side of the edge. Is it from the visualization tool?. I am not able to get like this. Attached is the plot from my visualization. I have turned on the "Arrow in log scale".
        Please let me know.
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        visual.PNG333.7 KB
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        volker_muehlhaus @ Leyo on Mar 6, 2014 12:39 PM
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        > {quote:title=Leyo wrote:}{quote}
        > In your plot, I could see "Red Big arrows" on the left side of the edge. Is it from the visualization tool?.
        
        I added this manually to the pictures, to show where I expect the port excitation.
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        jeff0283 @ volker_muehlhaus on Jul 18, 2015 9:57 AM
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        > {quote:title=volker_muehlhaus wrote:}{quote}
        > > {quote:title=Leyo wrote:}{quote}
        > > 2. Cell2==>Polygon_Port. Port P1 is placed on the the added rectangle edge and reference offset applied. Simulation and current visualization are working fine. For some reason, I am not able to see much difference in the current visualization of step 1 and 2. In Step 2, current should be limited to the width of the added rectangle?
        >
        > With my modified position of P2, you can now see the difference. See attached picture current_addpolygon.
        >
        > > 3. Cell 3 ==>Polyline_Port. Trying to do the "EDGE PORT with Polyline". Drew the polyline on the left edge of the trace. Added port P1 and snapped to the trace( And polyline). Selected the polyline. From "Edit menu selected "EDGE/Area pin". Clicked "Select Pin" and selected Pin1 and apply. Is this the correct way to assign the edge/area pin?.
        >
        > This does "something", but I would have used a polygon (area) instead of a polyline (line). It seems that ADS is confused by using a line. If we do the same thing with a polygon (rectangle), it works and does not cause trouble in the current viewer. In the attached workspace, see model "areapin".
        >
        
        Hi volker:
        What's the difference of the result between 2. and 3.??
        Since the LDMOS's tab is on the top metal in terms of the real circuit board, I think the area pin(3) is more similar to the physical result than the pin on the added rectangle plus reference offset(2)?? Is that right??
        
        Thanks for your reply.~
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volker_muehlhaus Mar 6, 2014 10:25 AM
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The big arrows are added later by me (in Powerpoint) to show where I expect the excitation.
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Ground reference for internal port_momentum

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