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Difficulties, while creating layout in ADS 2009.

Question asked by btv_murthy@rediffmail.com on Aug 30, 2013
Latest reply on Sep 3, 2013 by btv_murthy@rediffmail.com
Dear Sir,

(1) I have  taken ATF 54143 transistor. It is 4 pin IC , two sources are present diagonally opposite to each other. When I connected the some thing two sides of the two sources of the ATF 54143 transistor and generated layout. In layout generation, ATF 54143 transistor layout  generated, two sources are generating side by side. Sources are not generating diagonally opposite to each other, they are adjacent to each other in the layout generation. How to generate the ATF 54143 transistor  two sources diagonally opposite to each other. One more thing physically transistors two sources are diagonally opposite to each other, if layout generation comes side by side two sources, while fabrication it is difficulty.Now how to get the two sources diagonally opposite to each other in layout generation. I have shown below the images of ATF54143_SCHEMATIC and ATF54143_LAYOUT.


(2) One more difficulty, I have. I want to generate the two layers top layer and bottom layers in layout generation. I want to connect the VIA HOLE from top layer to bottom layer . Where is VIA HOLE available in ADS 2009. How we can generate  bottom and top layers in ADS 2009 and how we can connect the VIA HOLE from top to bottom layer through the substrate. I have searched the VIA HOLE in the palette, couldn't find out.
                     I have noticed in the example from C:\ADS2009\examples\MW_Ckts\LNA_1GHz_prj, but they didn't use the VIA HOLE connection and bottom conductor.  My question is , how to generate the top and bottom layers and connect the VIA HOLE from top to bottom through the substrate with some thickness. Can you help me to sort out  these difficulty.  

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