Dear Sir,

I have designed Low noise amplifier at 1.3 GHz , obtained gain, noise figure and stability using linear transistor model using ADS2009 ( transistor model is AVAGO ATF 54143 at Vds = 3V and Id = 60 mA). I wanted to measure IIP3, OIP3 and P1 dB compression point to measure non linearity of the low noise amplifier. I have connected linear device model to biasing , input and output matching circuit and obtained the gain, noise figure and stability. But same input and output matching and biasing connected for the nonlinear device model , ADS 54143 non linear device model downloaded from the website( Which ever input and output matching,biasing connected for linear device model). But results of the linear and nonlinear device model are not same, entirely different results are coming. I don't know, where I could do the mistake. Can you anybody help me to get the same results for both linear and nonlinear.

I have designed Low noise amplifier at 1.3 GHz , obtained gain, noise figure and stability using linear transistor model using ADS2009 ( transistor model is AVAGO ATF 54143 at Vds = 3V and Id = 60 mA). I wanted to measure IIP3, OIP3 and P1 dB compression point to measure non linearity of the low noise amplifier. I have connected linear device model to biasing , input and output matching circuit and obtained the gain, noise figure and stability. But same input and output matching and biasing connected for the nonlinear device model , ADS 54143 non linear device model downloaded from the website( Which ever input and output matching,biasing connected for linear device model). But results of the linear and nonlinear device model are not same, entirely different results are coming. I don't know, where I could do the mistake. Can you anybody help me to get the same results for both linear and nonlinear.

The second schematic is the packaged device model for the transistor. This has a disconnected wire on the source so this will cause incorrect results. It also looks like you are doing an s-parameter simulation on the device but without any biasing. This is also incorrect. This model for the transistor will only work, for any simulation, if it is fully biased at the required operating point.

In the third schematic it looks like you are reusing the dataset results generated from the second schematic as the device model. As explained above this model is not biased and all that is being recorded in the dataset is simple s-parameters at this invalid/non-operational bias point. You should really be placing the symbol for the actual device model for the transistor, without the terms and using ports, as a subnetwork into the third schematic.