I created my ATC2 core for my Xilinx Virtex 4 FPGA and I forgot to assign some of the pins to the core, can I add those signals to the core or do I have to redo everything?
You can still use Xilinx FPGA editor to route new input signals to the ATC2 core. However, a new .cdc file is not produced, so you will need to update the new signal name on the logic analyzer. Alternatively, you can change input signals by recompiling the FPGA design with a new ATC2 core or new signal connections to the core.
If I use FPGA editor, the signals being presented to the logic analyzer are now different from what the .cdc file specified so what you have to is On the logic analyzer, you can manually rename whatever signal names you need to. In the FPGA dynamic probe application, simply activate the bank where the signal name change is needed. Then in the logic analyzer setup, listing, or waveform menu, modify the previous signal name with the new one you have routed out with FPGA Editor. The FPGA dynamic probe application will remember name changes you made for each bank signal.
where the signal name change is needed. Then in the logic analyzer setup, listing, or waveform menu, modify the previous signal name with the new one you have routed out with FPGA Editor. The FPGA dynamic probe application will remember name changes you made for each bank signal.