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How to maximize state analyzer capture depth?

Question asked by mike.kirk on Jan 30, 2012
Latest reply on Jan 30, 2012 by algoss

I have two 16557D modules in my 16702b mainframe.  These offer 2Msa capture depth per channel.

I am capturing a serial data stream (6 MHz gated clock, frame sync and data => 3 signals, channels 0,1,2) over time with a faster (24 MHz) state state J clock input.

Is there an app. note, manual/guide or other document that offers ideas on how sequentially trigger other channels to go beyond the 2 MSa capture limit?
e.g. can I remap the unused channels (3-15) on this pod to store more of the signals on channels 0-2? Or possibly expand using other pods?

Best case would be something like:   4 pods x 16 channels per pod x 2 MSa depth = 96 MSa of storage / 3 signals (clk/sync/data) => 32 Msa of capture depth
With 2 16557d cards, that could be doubled to 64MSa depth

Or maybe a serial to parallel converter technique that would take 8/16 serial bits and store them in parallel in the capture memory?

As far as recovering the "compressed" data, I can write a post-processing tool that will extract the captured data in the correct order of capture.